Current traffic distribution between memory levels indicates possible inefficient memory access patterns present. Run a Memory Access Patterns analysis to confirm.
- Data transferred between L1 and L2 cache levels (in cache lines) exceed CARM traffic between CPU registers and Memory subsystem (in bytes).
This can be due to inefficient memory access pattern and cache line utilization. In this case, you only access a single element from a full cache line stored in L1. - Memory-Level Roofline