The bottleneck depends heavily on the fused multiply-add (FMA) computational unit. The bottleneck depends greatly on the accessed computational unit. The performance of the loop is also bounded by the DRAM bandwidth.
The performance of the loop is also bounded by the private cache bandwidth.
The performance of the loop is also bounded by the L1 bandwidth.
The performance of the loop is also bounded by the L2 bandwidth.
The performance of the loop is also bounded by the L3 bandwidth.
The performance of the loop is also bounded by the L4 bandwidth.
The performance of the loop is also bounded by the DRAM bandwidth.
The performance of the loop is also bounded by the MCDRAM bandwidth.
To improve performance: Switch from %c_isa% to %b_isa% - the highest available instruction set architecture (ISA). Eliminate inefficient memory access patterns. %traits% instructions might degrade performance. The loop is scalar. To fix: Vectorize the loop.
The performance of the loop is also bounded by the private cache bandwidth.
The performance of the loop is also bounded by the L1 bandwidth.
The performance of the loop is also bounded by the L2 bandwidth.
The performance of the loop is also bounded by the L3 bandwidth.
The performance of the loop is also bounded by the L4 bandwidth.
The performance of the loop is also bounded by the DRAM bandwidth.
The performance of the loop is also bounded by the MCDRAM bandwidth.
To improve performance: Switch from %c_isa% to %b_isa% - the highest available instruction set architecture (ISA). Eliminate inefficient memory access patterns. %traits% instructions might degrade performance. The loop is scalar. To fix: Vectorize the loop.
- Data transferred between L1 and L2 cache levels (in cache lines) exceed CARM traffic between CPU registers and Memory subsystem (in bytes).
This can be due to inefficient memory access pattern and cache line utilization. In this case, you only access a single element from a full cache line stored in L1. - Memory-Level Roofline
- Vectorization Resources for Intel® Advisor Users