# Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.27
# 05/22/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	INST_RETIRED.ANY	Counts the total number of instructions retired. (Fixed event)	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0	0x00
0x00	0x02	CPU_CLK_UNHALTED.CORE	Counts the number of unhalted core clock cycles. (Fixed event)	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	NA	0x00
0x00	0x02	CPU_CLK_UNHALTED.THREAD	Counts the number of unhalted core clock cycles. (Fixed event)	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	NA	0x00
0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	NA	0x00
0x03	0x01	LD_BLOCKS.DATA_UNKNOWN	Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x03	0x04	LD_BLOCKS.4K_ALIAS	This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x01
0x03	0x04	LD_BLOCKS.ADDRESS_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x04	0x01	MEM_SCHEDULER_BLOCK.ST_BUF	Counts the number of cycles that uops are blocked due to a store buffer full condition.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x02	MEM_SCHEDULER_BLOCK.LD_BUF	Counts the number of cycles that uops are blocked due to a load buffer full condition.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x04	MEM_SCHEDULER_BLOCK.RSV	Counts the number of cycles that uops are blocked due to an RSV full condition.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x07	MEM_SCHEDULER_BLOCK.ALL	Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x81	LD_HEAD.L1_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x84	LD_HEAD.ST_ADDR_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x90	LD_HEAD.DTLB_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xa0	LD_HEAD.PGWALK_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xc0	LD_HEAD.OTHER_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xf4	LD_HEAD.L1_BOUND_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xff	LD_HEAD.ANY_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses to any page size.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x0e	0x00	UOPS_ISSUED.ANY	Counts the number of uops issued by the front end every cycle.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x41	LONGEST_LAT_CACHE.MISS	Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x01	MEM_BOUND_STALLS.LOAD_L2_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x02	MEM_BOUND_STALLS.LOAD_LLC_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x04	MEM_BOUND_STALLS.LOAD_DRAM_HIT	Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x07	MEM_BOUND_STALLS.LOAD	Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x08	MEM_BOUND_STALLS.IFETCH_L2_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x10	MEM_BOUND_STALLS.IFETCH_LLC_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x20	MEM_BOUND_STALLS.IFETCH_DRAM_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x38	MEM_BOUND_STALLS.IFETCH	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	NA	0x00
0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Counts the number of unhalted core clock cycles.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	NA	0x00
0x3c	0x01	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	NA	0x00
0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to any page size.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x00	TOPDOWN_FE_BOUND.ALL	Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x01	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x02	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x04	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x08	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	TOPDOWN_FE_BOUND.ITLB	Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x20	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x40	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x72	TOPDOWN_FE_BOUND.FRONTEND_LATENCY	Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x80	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x8d	TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH	Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x00	TOPDOWN_BAD_SPECULATION.ALL	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x01	TOPDOWN_BAD_SPECULATION.NUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x02	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x03	TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x04	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x00	TOPDOWN_BE_BOUND.ALL	Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x01	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x02	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x08	TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x10	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x20	TOPDOWN_BE_BOUND.REGISTER	Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x40	TOPDOWN_BE_BOUND.REORDER_BUFFER	Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x02	SERIALIZATION.NON_C01_MS_SCB	Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x04	SERIALIZATION.C01_MS_SCB	Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x02	ICACHE.MISSES	Counts the number of instruction cache misses.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x03	ICACHE.ACCESSES	Counts the number of requests to the instruction cache for one or more bytes of a cache line.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x01	ITLB_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x80	ITLB_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any type of response.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_MISS	Counts demand data reads that were not supplied by the L3 cache.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F84400001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_RFO.L3_MISS	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F84400002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.COREWB_M.ANY_RESPONSE	Counts modified writebacks from L1 cache and L2 cache that have any type of response.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10008	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.STREAMING_WR.ANY_RESPONSE	Counts streaming stores that have any type of response.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10800	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x4003C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x8003C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10003C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x10003C0002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT	Counts demand data reads that were supplied by the L3 cache.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F803C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F803C0002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_MISS_LOCAL	Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F84400001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xB7	0x01,0x02	OCR.DEMAND_RFO.L3_MISS_LOCAL	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]	0,1,2,3,4,5	0	100003	0x1a6,0x1a7	0x3F84400002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0xc0	0x00	INST_RETIRED.ANY_P	Counts the total number of instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	0	0x00
0xc2	0x00	UOPS_RETIRED.ALL	Counts the total number of uops retired.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x00	TOPDOWN_RETIRING.ALL	Counts the total number of consumed retirement slots.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x01	UOPS_RETIRED.MS	Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x02	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in MS flows.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x08	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x10	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired.	0,1,2,3,4,5	0,1,2,3,4,5	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc3	0x01	MACHINE_CLEARS.SMC	Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x20	MACHINE_CLEARS.PAGE_FAULT	Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x6f	MACHINE_CLEARS.SLOW	Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.	0,1,2,3,4,5	0,1,2,3,4,5	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x80	MACHINE_CLEARS.MRN_NUKE	Counts the number of machines clears due to memory renaming.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x7e	BR_INST_RETIRED.JCC	This event is deprecated. Refer to new event BR_INST_RETIRED.COND	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0x7e	BR_INST_RETIRED.COND	Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xbf	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xc0	BR_INST_RETIRED.NEAR_TAKEN	Counts the number of near taken branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xeb	BR_INST_RETIRED.NON_RETURN_IND	This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0xeb	BR_INST_RETIRED.INDIRECT	Counts the number of near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xf7	BR_INST_RETIRED.RETURN	This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0xf7	BR_INST_RETIRED.NEAR_RETURN	Counts the number of near RET branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xf9	BR_INST_RETIRED.CALL	This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0xf9	BR_INST_RETIRED.NEAR_CALL	Counts the number of near CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xfb	BR_INST_RETIRED.IND_CALL	This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0xfb	BR_INST_RETIRED.INDIRECT_CALL	Counts the number of near indirect CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xfd	BR_INST_RETIRED.REL_CALL	Counts the number of near relative CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0xfe	BR_INST_RETIRED.TAKEN_JCC	This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc4	0xfe	BR_INST_RETIRED.COND_TAKEN	Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x7e	BR_MISP_RETIRED.JCC	This event is deprecated. Refer to new event BR_MISP_RETIRED.COND	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc5	0x7e	BR_MISP_RETIRED.COND	Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x80	BR_MISP_RETIRED.NEAR_TAKEN	Counts the number of mispredicted near taken branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0xeb	BR_MISP_RETIRED.NON_RETURN_IND	This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc5	0xeb	BR_MISP_RETIRED.INDIRECT	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0xf7	BR_MISP_RETIRED.RETURN	Counts the number of mispredicted near RET branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0xfb	BR_MISP_RETIRED.IND_CALL	This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc5	0xfb	BR_MISP_RETIRED.INDIRECT_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0xfe	BR_MISP_RETIRED.TAKEN_JCC	This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x01
0xc5	0xfe	BR_MISP_RETIRED.COND_TAKEN	Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x4	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x80	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x40	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x20	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x10	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x8	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x200	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x05	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256	Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.	0,1	0	1000003	0x3F6	0x100	1	2	1	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x06	MEM_UOPS_RETIRED.STORE_LATENCY	Counts the number of stores uops retired. Counts with or without PEBS enabled.	0,1,2,3,4,5	0,1,2,3,4,5	1000003	0x00	0x00	1	2	0	5	0x53	1	0	0	1	1	0	0	0	0	0x00
0xd0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load uops retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x82	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store uops retired.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load uops retired that hit in the L2 cache.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Counts the number of load uops retired that hit in the L3 cache.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x80	MEM_LOAD_UOPS_RETIRED.DRAM_HIT	Counts the number of load uops retired that hit in DRAM.	0,1,2,3,4,5	0,1,2,3,4,5	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xe4	0x01	MISC_RETIRED.LBR_INSERTS	Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]	0,1,2,3,4,5	0	1000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	1	0	0x00
0xe4	0x01	LBR_INSERTS.ANY	This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]	0,1,2,3,4,5	0	1000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	1	0	0x01
0xe6	0x01	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3,4,5	0,1,2,3,4,5	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	NA	0x00
