# Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.27
# 05/22/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	NAME	DESCRIPTION	COUNTER	EVENT_STATUS	COUNTER_TYPE
iMC	0x00	0x00	UNC_MC0_RDCAS_COUNT_FREERUN	Counts every 64B read  request entering the Memory Controller 0 to DRAM (sum of all channels).	0	0x00	FREERUN
iMC	0x00	0x00	UNC_MC1_RDCAS_COUNT_FREERUN	Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).	3	0x00	FREERUN
iMC	0x00	0x00	UNC_MC0_WRCAS_COUNT_FREERUN	Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.	1	0x00	FREERUN
iMC	0x00	0x00	UNC_MC1_WRCAS_COUNT_FREERUN	Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.	4	0x00	FREERUN
iMC	0x01	0x00	UNC_M_CLOCKTICKS	Number of clocks	0,1,2,3,4	0x00	PGMABLE
iMC	0x02	0x00	UNC_M_VC0_REQUESTS_RD	Incoming VC0 read request	0,1,2,3,4	0x00	PGMABLE
iMC	0x03	0x00	UNC_M_VC0_REQUESTS_WR	Incoming VC0 write request	0,1,2,3,4	0x00	PGMABLE
iMC	0x04	0x00	UNC_M_VC1_REQUESTS_RD	Incoming VC1 read request	0,1,2,3,4	0x00	PGMABLE
iMC	0x05	0x00	UNC_M_VC1_REQUESTS_WR	Incoming VC1 write request	0,1,2,3,4	0x00	PGMABLE
iMC	0x0A	0x00	UNC_M_PREFETCH_RD	Incoming read prefetch request from IA.	0,1,2,3,4	0x00	PGMABLE
iMC	0x19	0x00	UNC_M_DRAM_THERMAL_HOT	Any Rank at Hot state	0,1,2,3,4	0x00	PGMABLE
iMC	0x1A	0x00	UNC_M_DRAM_THERMAL_WARM	Any Rank at Warm state	0,1,2,3,4	0x00	PGMABLE
iMC	0x1C	0x00	UNC_M_DRAM_PAGE_HIT_RD	incoming read request page status is Page Hit	0,1,2,3,4	0x00	PGMABLE
iMC	0x1D	0x00	UNC_M_DRAM_PAGE_EMPTY_RD	incoming read request page status is Page Empty	0,1,2,3,4	0x00	PGMABLE
iMC	0x1E	0x00	UNC_M_DRAM_PAGE_MISS_RD	incoming read request page status is Page Miss	0,1,2,3,4	0x00	PGMABLE
iMC	0x1F	0x00	UNC_M_DRAM_PAGE_HIT_WR	incoming write request page status is Page Hit	0,1,2,3,4	0x00	PGMABLE
iMC	0x20	0x00	UNC_M_DRAM_PAGE_EMPTY_WR	incoming write request page status is Page Empty	0,1,2,3,4	0x00	PGMABLE
iMC	0x21	0x00	UNC_M_DRAM_PAGE_MISS_WR	incoming write request page status is Page Miss	0,1,2,3,4	0x00	PGMABLE
iMC	0x22	0x00	UNC_M_CAS_COUNT_RD	Read CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x23	0x00	UNC_M_CAS_COUNT_WR	Write CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x24	0x00	UNC_M_ACT_COUNT_RD	ACT command for a read request sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x25	0x00	UNC_M_ACT_COUNT_WR	ACT command for a write request sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x26	0x00	UNC_M_ACT_COUNT_TOTAL	ACT command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x27	0x00	UNC_M_PRE_COUNT_PAGE_MISS	PRE command sent to DRAM for a read/write request	0,1,2,3,4	0x00	PGMABLE
iMC	0x28	0x00	UNC_M_PRE_COUNT_IDLE	PRE command sent to DRAM due to page table idle timer expiration	0,1,2,3,4	0x00	PGMABLE
