# Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.03
# 08/16/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	EQUAL	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	0x00	INST_RETIRED.ANY	Fixed Counter: Counts the number of instructions retired	32	32	2000003	0x00	0x00	1	2	0	0	0x53	0	1	1	0	0	0	0	0	0	32	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.CORE	Fixed Counter: Counts the number of unhalted core clock cycles	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.THREAD	Fixed Counter: Counts the number of unhalted core clock cycles	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	NA	0x00
0x00	0x03	0x00	CPU_CLK_UNHALTED.REF_TSC	Fixed Counter: Counts the number of unhalted reference clock cycles	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	NA	0x00
0x03	0x01	0x00	LD_BLOCKS.DATA_UNKNOWN	Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x02	0x00	LD_BLOCKS.STORE_FORWARD	Counts the number of retired loads that are blocked because its address partially overlapped with an older store.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x04	0x00	LD_BLOCKS.ADDRESS_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x01	0x00	MEM_SCHEDULER_BLOCK.ST_BUF	Counts the number of cycles that uops are blocked due to a store buffer full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x02	0x00	MEM_SCHEDULER_BLOCK.LD_BUF	Counts the number of cycles that uops are blocked due to a load buffer full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x04	0x00	MEM_SCHEDULER_BLOCK.RSV	Counts the number of cycles that uops are blocked due to an RSV full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x07	0x00	MEM_SCHEDULER_BLOCK.ALL	Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x81	0x00	LD_HEAD.L1_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x84	0x00	LD_HEAD.ST_ADDR_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x90	0x00	LD_HEAD.DTLB_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xa0	0x00	LD_HEAD.PGWALK_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xc0	0x00	LD_HEAD.OTHER_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xf4	0x00	LD_HEAD.L1_BOUND_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xff	0x00	LD_HEAD.ANY_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x02	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to load DTLB misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x04	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x0e	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x10	0x00	DTLB_LOAD_MISSES.WALK_PENDING	Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x20	0x00	DTLB_LOAD_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x0e	0x00	0x00	UOPS_ISSUED.ANY	Counts the number of uops issued by the front end every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x02	0x00	MISALIGN_MEM_REF.LOAD_PAGE_SPLIT	Counts misaligned loads that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x04	0x00	MISALIGN_MEM_REF.STORE_PAGE_SPLIT	Counts misaligned stores that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	0x00	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x01	0x00	MEM_BOUND_STALLS_LOAD.L2_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x35	0x01	0x00	MEM_BOUND_STALLS_IFETCH.L2_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.THREAD_P	Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x01	0x00	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	NA	0x00
0x49	0x0e	0x00	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to a 1G page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x10	0x00	DTLB_STORE_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x20	0x00	DTLB_STORE_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x00	0x00	TOPDOWN_FE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to front end stalls	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x01	0x00	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to ms	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x02	0x00	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x04	0x00	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x08	0x00	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	0x00	TOPDOWN_FE_BOUND.ITLB_MISS	Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	0x00	TOPDOWN_FE_BOUND.ITLB	This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0x71	0x20	0x00	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x40	0x00	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x72	0x00	TOPDOWN_FE_BOUND.FRONTEND_LATENCY	Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x80	0x00	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x8d	0x00	TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH	Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x72	0x00	0x00	TOPDOWN_RETIRING.ALL_P	Counts the number of consumed retirement slots.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x00	0x00	TOPDOWN_BAD_SPECULATION.ALL_P	Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x01	0x00	TOPDOWN_BAD_SPECULATION.NUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x02	0x00	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as  Memory Ordering Machine clears and MRN nukes	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x03	0x00	TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x04	0x00	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x00	0x00	TOPDOWN_BE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to backend stalls	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x01	0x00	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x02	0x00	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop).  This could be caused by RSV full or load/store buffer block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x08	0x00	TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x10	0x00	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x20	0x00	TOPDOWN_BE_BOUND.REGISTER	Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall.  A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x04	0x00	SERIALIZATION.C01_MS_SCB	Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x02	0x00	ICACHE.MISSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x03	0x00	ICACHE.ACCESSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x04	0x00	ITLB_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x0e	0x00	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x10	0x00	ITLB_MISSES.WALK_PENDING	Counts the number of page walks outstanding for iside in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc0	0x00	0x00	INST_RETIRED.ANY_P	Counts the number of instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0xc2	0x00	0x00	UOPS_RETIRED.ALL	Counts the total number of uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x01	0x00	UOPS_RETIRED.MS	Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in ms flows	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x08	0x00	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x10	0x00	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x01	0x00	MACHINE_CLEARS.SMC	Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x00	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	0x00	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	0x00	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x20	0x00	MACHINE_CLEARS.PAGE_FAULT	Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x6f	0x00	MACHINE_CLEARS.SLOW	Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0x7e	0x00	BR_INST_RETIRED.COND	Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xbf	0x00	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xc0	0x00	BR_INST_RETIRED.NEAR_TAKEN	Counts the number of near taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xdf	0x00	BR_INST_RETIRED.REL_JMP	Counts the number of near relative JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xeb	0x00	BR_INST_RETIRED.INDIRECT	Counts the number of near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xef	0x00	BR_INST_RETIRED.INDIRECT_JMP	Counts the number of near indirect JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xf7	0x00	BR_INST_RETIRED.NEAR_RETURN	Counts the number of near RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xf9	0x00	BR_INST_RETIRED.NEAR_CALL	Counts the number of near CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfb	0x00	BR_INST_RETIRED.INDIRECT_CALL	Counts the number of near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfd	0x00	BR_INST_RETIRED.REL_CALL	Counts the number of near relative CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfe	0x00	BR_INST_RETIRED.COND_TAKEN	Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x00	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x7e	0x00	BR_MISP_RETIRED.COND	Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x80	0x00	BR_MISP_RETIRED.NEAR_TAKEN	Counts the number of mispredicted near taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xeb	0x00	BR_MISP_RETIRED.INDIRECT	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xef	0x00	BR_MISP_RETIRED.INDIRECT_JMP	Counts the number of mispredicted near indirect JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xf7	0x00	BR_MISP_RETIRED.RETURN	Counts the number of mispredicted near RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xfb	0x00	BR_MISP_RETIRED.INDIRECT_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xfe	0x00	BR_MISP_RETIRED.COND_TAKEN	Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc6	0x10	0x00	FRONTEND_RETIRED.ITLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x01	0x00	FP_INST_RETIRED.32B_SP	Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x02	0x00	FP_INST_RETIRED.64B_DP	Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x04	0x00	FP_INST_RETIRED.128B_SP	Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x08	0x00	FP_INST_RETIRED.128B_DP	Counts the total number of  floating point retired instructions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x03	0x00	FP_FLOPS_RETIRED.ALL	Counts the number of all types of floating point operations per uop with all default weighting	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x02	0x00	ARITH.FPDIV_ACTIVE	Counts the number of cycles when any of the floating point dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x03	0x00	ARITH.DIV_ACTIVE	Counts the number of cycles when any of the floating point or integer dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x8	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x40	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x200	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x4	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x20	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x100	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x10	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x80	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x800	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1	0,1	1000003	0x3F6	0x400	0	2	1	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x06	0x00	MEM_UOPS_RETIRED.STORE_LATENCY	Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x21	0x00	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x41	0x00	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x42	0x00	MEM_UOPS_RETIRED.SPLIT_STORES	Counts the number of retired split store uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x81	0x00	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x82	0x00	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd1	0x01	0x00	MEM_LOAD_UOPS_RETIRED.L1_HIT	Counts the number of load ops retired that hit the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x02	0x00	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load ops retired that hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x20	0x00	MEM_LOAD_UOPS_RETIRED.WCB_HIT	Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x40	0x00	MEM_LOAD_UOPS_RETIRED.L1_MISS	Counts the number of load ops retired that miss in the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x01	0x00	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
