##########################################################################
# SEP Uncore Event File: UNC_SOC_Memory_DDR1_BW.txt
# Copyright(c)2014 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Mon Aug 25 13:42:09 2014
# Target: AVN-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 1103286
# GROUP_NAME       : UNC_SOC_Memory_DDR1_BW
# GROUP_DESC       : Counts requests of size 32 bytes and 64 bytes to memory, for memory channel 1. Determine memory bandwidth by multiplying event count by the request size (32 or 64 bytes).
# EVENT_ID         : 1103231
# EVENT_NAME       : DDR_Chan1_Read32B
# EVENT_DESC       : Counts memory read requests of size 32 bytes to memory channel 1.
# EVENT_COUNTER    : 0
# EVENT_ID         : 1103232
# EVENT_NAME       : DDR_Chan1_Read64B
# EVENT_DESC       : Counts memory read requests of size 64 bytes to memory channel 1.
# EVENT_COUNTER    : 1
# EVENT_ID         : 1103233
# EVENT_NAME       : DDR_Chan1_Write32B
# EVENT_DESC       : Counts memory write requests of size 32 bytes to memory channel 1.
# EVENT_COUNTER    : 2
# EVENT_ID         : 1103234
# EVENT_NAME       : DDR_Chan1_Write64B
# EVENT_DESC       : Counts memory write requests of size 64 bytes to memory channel 1.
# EVENT_COUNTER    : 3
# CLOCK_COUNTER    : 4

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000607	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x00000708	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A8	0x03C01404	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000AC	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B0	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E84	0x00001314	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E80	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E88	0x00001415	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000D884	0x000000A1	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000D880	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000D888	0x00000001	0xFFFFFFFF	25	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000008	0x00F80402	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000000C	0x00F80602	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000010	0x00F80502	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000014	0x00F80702	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000018	0x00000003	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000060	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000070	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000120	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000121	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00000122	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000005C	0x00000123	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000006C	0x00002124	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000064	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000074	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010120	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110121	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x02110122	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000058	0x02110123	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000068	0x00110000	0xFFFFFFFF	24	1
