##########################################################################
# SEP Uncore Event File: UNC_SOC_Module3_BW.txt
# Copyright(c)2014 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Mon Aug 25 13:42:09 2014
# Target: AVN-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 1103260
# GROUP_NAME       : UNC_SOC_Module3_BW
# GROUP_DESC       : Counts bandwidth events for Silvermont module 2. Determine bandwidth between Silvermont module 2 and memory by multiplying event count by the request size (32 or 64 bytes).
# EVENT_ID         : 1103283
# EVENT_NAME       : Mod3_ReadPartial
# EVENT_DESC       : Counts all module 3 read transactions of any data size request. This event count is inclusive of partial, 32 byte and 64 byte transactions.
# EVENT_COUNTER    : 0
# EVENT_ID         : 1103193
# EVENT_NAME       : Mod3_Read32B
# EVENT_DESC       : Counts memory read requests of size 32 bytes from Silvermont module 3.
# EVENT_COUNTER    : 1
# EVENT_ID         : 1103194
# EVENT_NAME       : Mod3_Read64B
# EVENT_DESC       : Counts memory read requests of size 64 bytes from Silvermont module 3.
# EVENT_COUNTER    : 2
# EVENT_ID         : 1103284
# EVENT_NAME       : Mod3_WritePartial
# EVENT_DESC       : Counts all module 3 write transactions of any data size request. This event count is inclusive of partial, 32 byte and 64 byte transactions.
# EVENT_COUNTER    : 3
# EVENT_ID         : 1103195
# EVENT_NAME       : Mod3_Write32B
# EVENT_DESC       : Counts memory write requests of size 32 bytes from Silvermont module 3.
# EVENT_COUNTER    : 4
# EVENT_ID         : 1103196
# EVENT_NAME       : Mod3_Write64B
# EVENT_DESC       : Counts memory write requests of size 64 bytes from Silvermont module 3.
# EVENT_COUNTER    : 5
# CLOCK_COUNTER    : 6

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000607	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x00000708	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000008C	0x00000809	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A8	0x00C02C02	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000AC	0x0000440A	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B0	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E84	0x00003031	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E80	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E88	0x00003132	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00003E8C	0x00003233	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009904	0x00000304	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009900	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009908	0x00000405	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000990C	0x00000506	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009684	0x00000004	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009680	0x00000001	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009688	0x00000005	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000968C	0x00000006	0xFFFFFFFF	25	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000008	0x00FC0302	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000000C	0x00F90602	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000010	0x00F50A02	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000014	0x00EE1102	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000018	0x00EB1402	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000001C	0x00E71802	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000020	0x00000003	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000060	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000070	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x10000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000090	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000120	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000121	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00000122	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000005C	0x00000123	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000006C	0x00000124	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000007C	0x00000125	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000008C	0x00002126	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000064	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000074	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000094	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010120	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110121	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x02110122	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000058	0x02110123	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000068	0x02110124	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000078	0x02110125	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x00110000	0xFFFFFFFF	24	1
