# Performance Monitoring Events for 5th Generation Intel(R) Core(TM) Processor Based on the Broadwell-DE Microarchitecture - V12
# 07/16/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	EVENT_STATUS
IRP	0x0	0x0	UNC_I_CLOCKTICKS	Clocks in the IRP	0,1	na	0	0x00
IRP	0x1	0x0	UNC_I_RxR_BL_DRS_INSERTS	BL Ingress Occupancy - DRS	0,1	na	0	0x00
IRP	0x12	0x1	UNC_I_CACHE_TOTAL_OCCUPANCY.ANY	Total Write Cache Occupancy; Any Source	0,1	na	0	0x00
IRP	0x12	0x2	UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE	Total Write Cache Occupancy; Select Source	0,1	na	0	0x00
IRP	0x13	0x1	UNC_I_COHERENT_OPS.PCIRDCUR	Coherent Ops; PCIRdCur	0,1	na	0	0x00
IRP	0x13	0x10	UNC_I_COHERENT_OPS.PCITOM	Coherent Ops; PCIItoM	0,1	na	0	0x00
IRP	0x13	0x2	UNC_I_COHERENT_OPS.CRD	Coherent Ops; CRd	0,1	na	0	0x00
IRP	0x13	0x20	UNC_I_COHERENT_OPS.PCIDCAHINT	Coherent Ops; PCIDCAHin5t	0,1	na	0	0x00
IRP	0x13	0x4	UNC_I_COHERENT_OPS.DRD	Coherent Ops; DRd	0,1	na	0	0x00
IRP	0x13	0x40	UNC_I_COHERENT_OPS.WBMTOI	Coherent Ops; WbMtoI	0,1	na	0	0x00
IRP	0x13	0x8	UNC_I_COHERENT_OPS.RFO	Coherent Ops; RFO	0,1	na	0	0x00
IRP	0x13	0x80	UNC_I_COHERENT_OPS.CLFLUSH	Coherent Ops; CLFlush	0,1	na	0	0x00
IRP	0x14	0x1	UNC_I_MISC0.FAST_REQ	Misc Events - Set 0; Fastpath Requests	0,1	na	0	0x00
IRP	0x14	0x10	UNC_I_MISC0.2ND_ATOMIC_INSERT	Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary	0,1	na	0	0x00
IRP	0x14	0x2	UNC_I_MISC0.FAST_REJ	Misc Events - Set 0; Fastpath Rejects	0,1	na	0	0x00
IRP	0x14	0x20	UNC_I_MISC0.FAST_XFER	Misc Events - Set 0; Fastpath Transfers From Primary to Secondary	0,1	na	0	0x00
IRP	0x14	0x4	UNC_I_MISC0.2ND_RD_INSERT	Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary	0,1	na	0	0x00
IRP	0x14	0x40	UNC_I_MISC0.PF_ACK_HINT	Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary	0,1	na	0	0x00
IRP	0x14	0x8	UNC_I_MISC0.2ND_WR_INSERT	Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary	0,1	na	0	0x00
IRP	0x14	0x80	UNC_I_MISC0.PF_TIMEOUT	Misc Events - Set 0; Prefetch TimeOut	0,1	na	0	0x00
IRP	0x15	0x1	UNC_I_MISC1.SLOW_I	Misc Events - Set 1; Slow Transfer of I Line	0,1	na	0	0x00
IRP	0x15	0x10	UNC_I_MISC1.LOST_FWD	Misc Events - Set 1	0,1	na	0	0x00
IRP	0x15	0x2	UNC_I_MISC1.SLOW_S	Misc Events - Set 1; Slow Transfer of S Line	0,1	na	0	0x00
IRP	0x15	0x20	UNC_I_MISC1.SEC_RCVD_INVLD	Misc Events - Set 1; Received Invalid	0,1	na	0	0x00
IRP	0x15	0x4	UNC_I_MISC1.SLOW_E	Misc Events - Set 1; Slow Transfer of E Line	0,1	na	0	0x00
IRP	0x15	0x40	UNC_I_MISC1.SEC_RCVD_VLD	Misc Events - Set 1; Received Valid	0,1	na	0	0x00
IRP	0x15	0x8	UNC_I_MISC1.SLOW_M	Misc Events - Set 1; Slow Transfer of M Line	0,1	na	0	0x00
IRP	0x15	0x80	UNC_I_MISC1.DATA_THROTTLE	Misc Events - Set 1; Data Throttled	0,1	na	0	0x00
IRP	0x16	0x1	UNC_I_TRANSACTIONS.READS	Inbound Transaction Count; Reads	0,1	na	0	0x00
IRP	0x16	0x10	UNC_I_TRANSACTIONS.ATOMIC	Inbound Transaction Count; Atomic	0,1	na	0	0x00
IRP	0x16	0x2	UNC_I_TRANSACTIONS.WRITES	Inbound Transaction Count; Writes	0,1	na	0	0x00
IRP	0x16	0x20	UNC_I_TRANSACTIONS.OTHER	Inbound Transaction Count; Other	0,1	na	0	0x00
IRP	0x16	0x4	UNC_I_TRANSACTIONS.RD_PREF	Inbound Transaction Count; Read Prefetches	0,1	na	0	0x00
IRP	0x16	0x40	UNC_I_TRANSACTIONS.ORDERINGQ	Inbound Transaction Count; Select Source	0,1	IRPFilter[4:0]	0	0x00
IRP	0x16	0x8	UNC_I_TRANSACTIONS.WR_PREF	Inbound Transaction Count; Write Prefetches	0,1	na	0	0x00
IRP	0x17	0x1	UNC_I_SNOOP_RESP.MISS	Snoop Responses; Miss	0,1	na	0	0x00
IRP	0x17	0x10	UNC_I_SNOOP_RESP.SNPCODE	Snoop Responses; SnpCode	0,1	na	0	0x00
IRP	0x17	0x2	UNC_I_SNOOP_RESP.HIT_I	Snoop Responses; Hit I	0,1	na	0	0x00
IRP	0x17	0x20	UNC_I_SNOOP_RESP.SNPDATA	Snoop Responses; SnpData	0,1	na	0	0x00
IRP	0x17	0x4	UNC_I_SNOOP_RESP.HIT_ES	Snoop Responses; Hit E or S	0,1	na	0	0x00
IRP	0x17	0x40	UNC_I_SNOOP_RESP.SNPINV	Snoop Responses; SnpInv	0,1	na	0	0x00
IRP	0x17	0x8	UNC_I_SNOOP_RESP.HIT_M	Snoop Responses; Hit M	0,1	na	0	0x00
IRP	0x18	0x0	UNC_I_TxR_AD_STALL_CREDIT_CYCLES	No AD Egress Credit Stalls	0,1	na	0	0x00
IRP	0x19	0x0	UNC_I_TxR_BL_STALL_CREDIT_CYCLES	No BL Egress Credit Stalls	0,1	na	0	0x00
IRP	0x2	0x0	UNC_I_RxR_BL_NCB_INSERTS	BL Ingress Occupancy - NCB	0,1	na	0	0x00
IRP	0x3	0x0	UNC_I_RxR_BL_NCS_INSERTS	BL Ingress Occupancy - NCS	0,1	na	0	0x00
IRP	0x4	0x0	UNC_I_RxR_BL_DRS_CYCLES_FULL	UNC_I_RxR_BL_DRS_CYCLES_FULL	0,1	na	0	0x00
IRP	0x5	0x0	UNC_I_RxR_BL_NCB_CYCLES_FULL	UNC_I_RxR_BL_NCB_CYCLES_FULL	0,1	na	0	0x00
IRP	0x6	0x0	UNC_I_RxR_BL_NCS_CYCLES_FULL	UNC_I_RxR_BL_NCS_CYCLES_FULL	0,1	na	0	0x00
IRP	0x7	0x0	UNC_I_RxR_BL_DRS_OCCUPANCY	UNC_I_RxR_BL_DRS_OCCUPANCY	0,1	na	0	0x00
IRP	0x8	0x0	UNC_I_RxR_BL_NCB_OCCUPANCY	UNC_I_RxR_BL_NCB_OCCUPANCY	0,1	na	0	0x00
IRP	0x9	0x0	UNC_I_RxR_BL_NCS_OCCUPANCY	UNC_I_RxR_BL_NCS_OCCUPANCY	0,1	na	0	0x00
IRP	0xA	0x0	UNC_I_RxR_AK_INSERTS	AK Ingress Occupancy	0,1	na	0	0x00
IRP	0xD	0x0	UNC_I_TxR_REQUEST_OCCUPANCY	Outbound Request Queue Occupancy	0,1	na	0	0x00
IRP	0xE	0x0	UNC_I_TxR_DATA_INSERTS_NCB	Outbound Read Requests	0,1	na	0	0x00
IRP	0xF	0x0	UNC_I_TxR_DATA_INSERTS_NCS	Outbound Read Requests	0,1	na	0	0x00
