# Performance Monitoring Events for 5th Generation Intel(R) Core(TM) Processor - V30
# 07/16/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	NAME	DESCRIPTION	COUNTER	eLLC_PRESENT	EVENT_STATUS
NCU	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	FIXED	0	0x00
ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.	0	0	0x00
ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST	Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;	0	0	0x00
ARB	0x80	0x02	UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT	Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.	0	0	0x00
ARB	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.	0,1	0	0x00
ARB	0x81	0x02	UNC_ARB_TRK_REQUESTS.DRD_DIRECT	Number of Core coherent Data Read entries allocated in DirectData mode	0,1	0	0x00
ARB	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Number of Writes allocated - any write transactions: full/partials writes and evictions.	0,1	0	0x00
ARB	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.	0,1	0	0x00
