##########################################################################
# SEP Uncore Event File: UNC_SOC_DDR0_Page_Hit_Miss.txt
# Copyright(c)2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Sept  10 2015
# Target: BXTP-A0
# Revision: 1.4-4.6.1.0
##########################################################################


# EVENT INFORMATION

# GROUP_ID         : 1391510
# GROUP_NAME       : UNC_SOC_DDR0_Page_Hit_Miss
# GROUP_DESC       : Counts DRAM page hit and miss events for the DDR unit.
# EVENT_ID         : 1385944
# EVENT_NAME       : DDR0_Activate
# EVENT_DESC       : Counts the number of activates commands issued to DDR unit.
# EVENT_COUNTER    : 0
# EVENT_ID         : 1391459
# EVENT_NAME       : DDR0_CAS_Read
# EVENT_DESC       : Counts the number of CAS read commands issued to DDR unit.
# EVENT_COUNTER    : 1
# EVENT_ID         : 1392345
# EVENT_NAME       : DDR0_CAS_Write
# EVENT_DESC       : Counts the number of CAS write commands issued to DDR unit.
# EVENT_COUNTER    : 2
# EVENT_ID         : 1385946
# EVENT_NAME       : DDR0_Precharge_Cmd0
# EVENT_DESC       : Counts the number of precharge command 0 issued for DDR unit. This count should be summed with the precharge command 1 count for the total precharge count to this DDR unit.
# EVENT_COUNTER    : 3
# EVENT_ID         : 1385947
# EVENT_NAME       : DDR0_Precharge_Cmd1
# EVENT_DESC       : Counts the number of precharge command 1 issued for DDR unit. This count should be summed with the precharge command 0 count for the total precharge count to this DDR unit.
# EVENT_COUNTER    : 4
# CLOCK_COUNTER    : 5

# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>

# SOC CONFIGURATION

MEM	0	0	2	32	WRITE	NPKBAR	0x00000090	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00000080	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020080	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020084	0x00000607	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020088	0x00000708	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200ac	0x03c03001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200b0	0x00002800	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200b4	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec04	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec08	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee04	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee08	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e600	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e604	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e608	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f480	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f484	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f488	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e400	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e404	0x0000070c	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e408	0x0000070b	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027080	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027084	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00000090	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000000e0	0x01000000	0xFFFFFFFF

# COUNTER CONFIGURATION

MEM	0	0	2	32	WRITE	NPKBAR	0x00005000	0x00008000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a8	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005008	0x00000043	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000500c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005010	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005014	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005018	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000501c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005020	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005024	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005034	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005030	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000502c	0x00000100	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005028	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005044	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005040	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000503c	0x00000101	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005038	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005054	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005050	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000504c	0x00000104	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005048	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005064	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005060	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000505c	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005058	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005074	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005070	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000506c	0x00000103	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005068	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005084	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005080	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000507c	0x00000120	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005078	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005094	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005090	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000508c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005088	0x00100000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a4	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a0	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000509c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005098	0x00100000	0xFFFFFFFF

