##########################################################################
# SEP Uncore Event File: UNC_SOC_DDR_Self_Refresh.txt
# Copyright(c)2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Sept  10 2015
# Target: BXTP-A0
# Revision: 1.4-4.6.1.0
##########################################################################


# EVENT INFORMATION

# GROUP_ID         : 1391506
# GROUP_NAME       : UNC_SOC_DDR_Self_Refresh
# GROUP_DESC       : Counts the number of clock cycles that memory is in self-refresh.
# EVENT_ID         : 1385952
# EVENT_NAME       : DDR0_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that the DDR unit spends in self-imposed self-refresh.
# EVENT_COUNTER    : 0
# EVENT_ID         : 1391471
# EVENT_NAME       : DDR1_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that the DDR unit spends in self-imposed self-refresh.
# EVENT_COUNTER    : 1
# EVENT_ID         : 1391485
# EVENT_NAME       : DDR2_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that the DDR unit spends in self-imposed self-refresh.
# EVENT_COUNTER    : 2
# EVENT_ID         : 1391499
# EVENT_NAME       : DDR3_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that the DDR unit spends in self-imposed self-refresh.
# EVENT_COUNTER    : 3
# CLOCK_COUNTER    : 4

# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>

# SOC CONFIGURATION

MEM	0	0	2	32	WRITE	NPKBAR	0x00000090	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00000080	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020080	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020084	0x00000607	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020088	0x00000708	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002008c	0x00000809	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00020090	0x0000090a	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200ac	0x05003004	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200b0	0x0000001c	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000200b4	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec04	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec08	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec0c	0x00000203	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ec10	0x00000304	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee04	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee08	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee0c	0x00000203	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002ee10	0x00000304	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e600	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e604	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e608	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e60c	0x00000203	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e610	0x00000304	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f480	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f484	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f488	0x00000607	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f48c	0x00000102	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002f490	0x00000708	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e400	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e404	0x0000070c	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002e408	0x00000406	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00026c00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00026c04	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027080	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027084	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002eb00	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002eb04	0x0000070c	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0002eb08	0x00000406	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00026c80	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00026c84	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027100	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00027104	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00000090	0x00000001	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000000e0	0x01000000	0xFFFFFFFF

# COUNTER CONFIGURATION

MEM	0	0	2	32	WRITE	NPKBAR	0x00005000	0x00008000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a8	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005008	0x00fe01C2	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000500c	0x00fd02C2	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005010	0x00fb04C2	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005014	0x00f708C2	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005018	0x000000C3	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000501c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005020	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005024	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005034	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005030	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000502c	0x00000120	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005028	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005044	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005040	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000503c	0x00000121	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005038	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005054	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005050	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000504c	0x00000122	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005048	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005064	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005060	0x10000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000505c	0x00000123	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005058	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005074	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005070	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000506c	0x00000124	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005068	0x00150000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005084	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005080	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000507c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005078	0x00100000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005094	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005090	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000508c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005088	0x00100000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a4	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x000050a0	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x0000509c	0x00000000	0xFFFFFFFF
MEM	0	0	2	32	WRITE	NPKBAR	0x00005098	0x00100000	0xFFFFFFFF

