# Performance Monitoring Events for Intel Atom(R) Processors based on Elkhart Lake microarchitecture - V1.05
# 03/08/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	DEFAULT	EM_TRIGGER	DATA_LA	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	INST_RETIRED.ANY	Counts the total number of instructions retired. (Fixed event)	32	32	2000003	0x00	0x00	1	2	0	5	0x53	1	1	0	0	0	0	0	0x00
0x00	0x02	CPU_CLK_UNHALTED.CORE	Counts the number of unhalted core clock cycles. (Fixed event)	33	33	2000003	0x00	0x00	0	2	0	5	0x53	1	1	0	0	0	0	NA	0x00
0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)	34	34	2000003	0x00	0x00	0	2	0	5	0x53	1	2	0	0	0	0	NA	0x00
0x03	0x01	LD_BLOCKS.DATA_UNKNOWN	Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x03	0x02	LD_BLOCKS.STORE_FORWARD	Counts the number of retired loads that are blocked because its address partially overlapped with an older store.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x03	0x04	LD_BLOCKS.4K_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x03	0x08	LD_BLOCKS.DTLB_MISS	Counts the number of retired loads that are blocked due to a first level TLB miss.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x03	0x10	LD_BLOCKS.ALL	Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to load DTLB misses to a 4K page.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x04	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x08	DTLB_LOAD_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to load DTLB misses to a 1G page.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses to any page size.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x10	DTLB_LOAD_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x08	0x80	DTLB_LOAD_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x0e	0x00	UOPS_ISSUED.ANY	Counts the number of uops issued by the front end every cycle.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x13	0x02	MISALIGN_MEM_REF.LOAD_PAGE_SPLIT	Counts the number of misaligned load uops that are 4K page splits.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x13	0x04	MISALIGN_MEM_REF.STORE_PAGE_SPLIT	Counts the number of misaligned store uops that are 4K page splits.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0x24	0x00	L2_REQUEST.ALL	Counts the total number of L2 Cache accesses. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x24	0x01	L2_REQUEST.MISS	Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x24	0x02	L2_REQUEST.HIT	Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x24	0x04	L2_REQUEST.REJECTS	Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x2e	0x41	LONGEST_LAT_CACHE.MISS	Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x30	0x00	L2_REJECT_XQ.ANY	Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x31	0x00	CORE_REJECT_L2Q.ANY	Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x01	C0_STALLS.LOAD_L2_HIT	This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x34	0x01	MEM_BOUND_STALLS.LOAD_L2_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x02	C0_STALLS.LOAD_LLC_HIT	This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x34	0x02	MEM_BOUND_STALLS.LOAD_LLC_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x04	C0_STALLS.LOAD_DRAM_HIT	This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x34	0x04	MEM_BOUND_STALLS.LOAD_DRAM_HIT	Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x07	MEM_BOUND_STALLS.LOAD	Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x08	MEM_BOUND_STALLS.IFETCH_L2_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x10	MEM_BOUND_STALLS.IFETCH_LLC_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x20	MEM_BOUND_STALLS.IFETCH_DRAM_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x38	MEM_BOUND_STALLS.IFETCH	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x34	0x40	MEM_BOUND_STALLS.STORE_BUFFER_FULL	Counts the number of cycles the core is stalled due to a store buffer being full.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x3c	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	5	0x53	0	1	0	0	0	0	NA	0x00
0x3c	0x01	CPU_CLK_UNHALTED.REF	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	5	0x53	0	3	0	0	0	0	NA	0x00
0x3c	0x01	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	5	0x53	0	3	0	0	0	0	NA	0x00
0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to store DTLB misses to a 4K page.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x04	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x08	DTLB_STORE_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to store DTLB misses to a 1G page.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to any page size.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x10	DTLB_STORE_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x20	DTLB_STORE_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x49	0x80	DTLB_STORE_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x4f	0x01	EPT.EPDE_HIT	Counts the number of Extended Page Directory Entry hits.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x4f	0x02	EPT.EPDE_MISS	Counts the number of Extended Page Directory Entry misses.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x4f	0x04	EPT.EPDPE_HIT	Counts the number of Extended Page Directory Pointer Entry hits.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x4f	0x08	EPT.EPDPE_MISS	Counts the number of Extended Page Directory Pointer Entry misses.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x4f	0x10	EPT.WALK_PENDING	Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x51	0x01	DL1.DIRTY_EVICTION	Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x63	0x00	BUS_LOCK.ALL	This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x57	0	0	0	0	0	0	NA	0x01
0x63	0x00	BUS_LOCK.SELF_LOCKS	Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x57	0	0	0	0	0	0	NA	0x00
0x63	0x01	BUS_LOCK.CYCLES_SELF_BLOCK	This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x63	0x01	BUS_LOCK.LOCK_CYCLES	Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x63	0x02	BUS_LOCK.CYCLES_OTHER_BLOCK	This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x63	0x02	BUS_LOCK.BLOCK_CYCLES	Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x00	TOPDOWN_FE_BOUND.ALL	Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x01	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x02	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x04	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x08	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x10	TOPDOWN_FE_BOUND.ITLB	Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x20	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x40	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x71	0x80	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x73	0x02	TOPDOWN_BAD_SPECULATION.MONUKE	This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x73	0x02	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x73	0x02	TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x73	0x04	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x73	0x06	TOPDOWN_BAD_SPECULATION.ALL	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x00	TOPDOWN_BE_BOUND.ALL	Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x01	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x02	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x04	TOPDOWN_BE_BOUND.STORE_BUFFER	This event is deprecated.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0x74	0x08	TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x10	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x20	TOPDOWN_BE_BOUND.REGISTER	Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x74	0x40	TOPDOWN_BE_BOUND.REORDER_BUFFER	Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x80	0x01	ICACHE.HIT	Counts the number of instruction cache hits.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x80	0x02	ICACHE.MISSES	Counts the number of instruction cache misses.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x80	0x03	ICACHE.ACCESSES	Counts the number of requests to the instruction cache for one or more bytes of a cache line.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x81	0x04	ITLB.FILLS	Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to instruction fetch misses to a 4K page.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x04	ITLB_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x08	ITLB_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to instruction fetch misses to a 1G page.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x10	ITLB_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x20	ITLB_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0x85	0x80	ITLB_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM	Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0400	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1001003C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT.SNOOP_MISS	Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1002003C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1004003C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1008003C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT.SNOOP_HITM	Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1010003C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS	Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM	Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE	Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x400000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PARTIAL_STREAMING_WR.L3_MISS	Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x402184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.FULL_STREAMING_WR.ANY_RESPONSE	Counts streaming stores which modify a full 64 byte cacheline that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x800000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.FULL_STREAMING_WR.L3_MISS	Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x802184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L1WB_M.ANY_RESPONSE	Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1000000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L1WB_M.L3_MISS	Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L2WB_M.ANY_RESPONSE	Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2000000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L2WB_M.L3_MISS	Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.ANY_RESPONSE	Counts all code reads that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.OUTSTANDING	Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.DRAM	Counts all code reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_MISS	Counts all code reads that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.ANY_RESPONSE	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE	0,1,2,3	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.OUTSTANDING	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING	0,1,2,3	0	100003	0x1a6	0x8000000000000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.DRAM	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_MISS	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.OUTSTANDING	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.DRAM	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_MISS	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.ANY_RESPONSE	Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.DRAM	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_MISS	Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.COREWB_M.ANY_RESPONSE	Counts modified writebacks from L1 cache and L2 cache that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3000000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.COREWB_M.OUTSTANDING	Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8003000000000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.COREWB_M.L3_MISS	Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.ANY_RESPONSE	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.DRAM	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_MISS	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.ANY_RESPONSE	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.OUTSTANDING	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.DRAM	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_MISS	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.ANY_RESPONSE	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.OUTSTANDING	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.DRAM	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_MISS	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE	Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10400	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.STREAMING_WR.ANY_RESPONSE	Counts streaming stores that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10800	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.STREAMING_WR.L3_MISS	Counts streaming stores that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000800	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.OTHER.ANY_RESPONSE	Counts miscellaneous requests, such as I/O accesses, that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x18000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.OTHER.L3_MISS	Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184008000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.ANY_RESPONSE	Counts uncached memory reads that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x100000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.OUTSTANDING	Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000100000000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.DRAM	Counts uncached memory reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x100184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_MISS	Counts uncached memory reads that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x102184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_WR.ANY_RESPONSE	Counts uncached memory writes that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x200000010000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_WR.L3_MISS	Counts uncached memory writes that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x202184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.DRAM	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.LOCAL_DRAM	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_RFO.LOCAL_DRAM	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.LOCAL_DRAM	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.LOCAL_DRAM	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.LOCAL_DRAM	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.LOCAL_DRAM	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.LOCAL_DRAM	Counts uncached memory reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x100184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.LOCAL_DRAM	Counts all code reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_MISS_LOCAL	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_MISS_LOCAL	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_MISS_LOCAL	Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.COREWB_M.L3_MISS_LOCAL	Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_MISS_LOCAL	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.STREAMING_WR.L3_MISS_LOCAL	Counts streaming stores that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000800	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.OTHER.L3_MISS_LOCAL	Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184008000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_MISS_LOCAL	Counts uncached memory reads that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x102184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_WR.L3_MISS_LOCAL	Counts uncached memory writes that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x202184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL	Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x402184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.FULL_STREAMING_WR.L3_MISS_LOCAL	Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x802184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L1WB_M.L3_MISS_LOCAL	Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L2WB_M.L3_MISS_LOCAL	Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2002184000000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_MISS_LOCAL	Counts all code reads that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PREFETCHES.ANY_RESPONSE	Counts all hardware and software prefetches that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10470	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PREFETCHES.L3_MISS	Counts all hardware and software prefetches that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000470	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.ANY_RESPONSE	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.OUTSTANDING	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).	0,1,2,3	0	100003	0x1a6	0x8000000000000477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.DRAM	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_MISS	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.LOCAL_DRAM	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_MISS_LOCAL	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2184000477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1003C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2003C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x4003C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_RD.L3_HIT	This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x01
0XB7	0x01,0x02	OCR.DEMAND_RFO.L3_HIT	Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0002	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_CODE_RD.L3_HIT	Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0004	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.COREWB_M.L3_HIT	Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3001F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_DATA_RD.L3_HIT	Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0010	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_RFO.L3_HIT	Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0020	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.HWPF_L2_CODE_RD.L3_HIT	Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0040	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.STREAMING_WR.L3_HIT	Counts streaming stores that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0800	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_RD.L3_HIT	Counts uncached memory reads that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x101F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.UC_WR.L3_HIT	Counts uncached memory writes that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x201F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.PARTIAL_STREAMING_WR.L3_HIT	Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x401F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.FULL_STREAMING_WR.L3_HIT	Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x801F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L1WB_M.L3_HIT	Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1001F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.L2WB_M.L3_HIT	Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x2001F803C0000	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.ALL_CODE_RD.L3_HIT	Counts all code reads that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0044	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT	Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0001	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0XB7	0x01,0x02	OCR.READS_TO_CORE.L3_HIT	Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1F803C0477	0	0	0	0	0x53	0	0	0	0	1	0	0	0x00
0xc0	0x00	INST_RETIRED.ANY_P	Counts the total number of instructions retired.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	5	0x53	0	1	0	0	0	0	0	0x00
0xc2	0x00	UOPS_RETIRED.ALL	Counts the total number of uops retired.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc2	0x00	TOPDOWN_RETIRING.ALL	Counts the total number of consumed retirement slots.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc2	0x01	UOPS_RETIRED.MS	Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc2	0x02	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in MS flows.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc2	0x08	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc2	0x10	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0x00
0xc3	0x00	MACHINE_CLEARS.ANY	Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc3	0x01	MACHINE_CLEARS.SMC	Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc3	0x04	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc3	0x08	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc3	0x20	MACHINE_CLEARS.PAGE_FAULT	Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.	0,1,2,3	0,1,2,3	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xc4	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0x7e	BR_INST_RETIRED.JCC	Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xbf	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xeb	BR_INST_RETIRED.NON_RETURN_IND	Counts the number of near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xf7	BR_INST_RETIRED.RETURN	Counts the number of near RET branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xf9	BR_INST_RETIRED.CALL	Counts the number of near CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xfb	BR_INST_RETIRED.IND_CALL	Counts the number of near indirect CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xfd	BR_INST_RETIRED.REL_CALL	Counts the number of near relative CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc4	0xfe	BR_INST_RETIRED.TAKEN_JCC	Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0x7e	BR_MISP_RETIRED.JCC	Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0xeb	BR_MISP_RETIRED.NON_RETURN_IND	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0xf7	BR_MISP_RETIRED.RETURN	Counts the number of mispredicted near RET branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0xfb	BR_MISP_RETIRED.IND_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xc5	0xfe	BR_MISP_RETIRED.TAKEN_JCC	Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	1	0	0x00
0xcb	0x01	HW_INTERRUPTS.RECEIVED	Counts the number of hardware interrupts received by the processor.	0,1,2,3	0,1,2,3	203	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xcb	0x02	HW_INTERRUPTS.MASKED	Counts the number of core cycles during which interrupts are masked (disabled).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xcb	0x04	HW_INTERRUPTS.PENDING_AND_MASKED	Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xcd	0x00	CYCLES_DIV_BUSY.ANY	This event is deprecated.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x01
0xcd	0x01	CYCLES_DIV_BUSY.IDIV	Counts the number of cycles the integer divider is busy.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xcd	0x02	CYCLES_DIV_BUSY.FPDIV	Counts the number of cycles the floating point divider is busy.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xd0	0x11	MEM_UOPS_RETIRED.DTLB_MISS_LOADS	Counts the number of load uops retired that miss in the second Level TLB.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x12	MEM_UOPS_RETIRED.DTLB_MISS_STORES	Counts the number of store uops retired that miss in the second level TLB.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x13	MEM_UOPS_RETIRED.DTLB_MISS	Counts the number of memory uops retired that missed in the second level TLB.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Counts the number of retired split store uops.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x43	MEM_UOPS_RETIRED.SPLIT	Counts the number of memory uops retired that were splits.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load uops retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x82	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store uops retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd0	0x83	MEM_UOPS_RETIRED.ALL	Counts the number of memory uops retired.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Counts the number of load uops retired that hit in the L1 data cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load uops retired that hit in the L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Counts the number of load uops retired that hit in the L3 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Counts the number of load uops retired that miss in the L1 data cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Counts the number of load uops retired that miss in the L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x20	MEM_LOAD_UOPS_RETIRED.HITM	Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xd1	0x80	MEM_LOAD_UOPS_RETIRED.DRAM_HIT	Counts the number of load uops retired that hit in DRAM.	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	1	0	0	0	0	0x00
0xe6	0x01	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe6	0x02	BACLEARS.INDIRECT	Counts the number of BACLEARS due to an indirect branch.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe6	0x04	BACLEARS.UNCOND	Counts the number of BACLEARS due to a direct, unconditional jump.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe6	0x08	BACLEARS.RETURN	Counts the number of BACLEARS due to a return branch.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe6	0x10	BACLEARS.COND	Counts the number of BACLEARS due to a conditional jump.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe8	0x00	BTCLEAR.ANY	Counts the total number of BTCLEARS.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
0xe9	0x01	DECODE_RESTRICTION.PREDECODE_WRONG	Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	NA	0x00
