# Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.10
# 07/18/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
M2M	0x02	0x01	0x00	0x00	0x00000000	UNC_M2M_RxC_AD_INSERTS	AD Ingress (from CMS) : AD Ingress (from CMS) Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x03	0x00	0x00	0x00	0x00000000	UNC_M2M_RxC_AD_OCCUPANCY	AD Ingress (from CMS) Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x17	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS	Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x17	0x07	0x00	0x00	0x00	UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE	Cycles when direct to core mode (which bypasses the CHA) was disabled	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x18	0x01	0x00	0x00	0x00000000	UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.PMM_HIT	Number of reads in which direct to core transaction was overridden : 2LM Hit?	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x18	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.CISGRESS	Number of reads in which direct to core transaction was overridden : Cisgress	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x18	0x03	0x00	0x00	0x00	UNC_M2M_DIRECT2CORE_TXN_OVERRIDE	Number of reads in which direct to core transaction were overridden	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x19	0x07	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPI_TAKEN	Messages sent direct to the Intel UPI	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1A	0x01	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS	Cycles when Direct2UPI was Disabled : Egress Ignored D2U	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1A	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS	Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1A	0x04	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS	Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1a	0x07	0x00	0x00	0x00	UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE	Cycles when direct to Intel UPI was disabled	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1b	0x07	0x00	0x00	0x00	UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS	Number of reads in which direct to Intel UPI transactions were overridden	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1C	0x01	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPITXN_OVERRIDE.PMM_HIT	Number of times a direct to UPI transaction was overridden.	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1C	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECT2UPI_TXN_OVERRIDE.CISGRESS	Number of times a direct to UPI transaction was overridden.	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1c	0x03	0x00	0x00	0x00	UNC_M2M_DIRECT2UPI_TXN_OVERRIDE	Number of reads that a message sent direct2 Intel UPI was overridden	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x01	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.DIRTY_I	Directory Hit : On Dirty Line in I State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.DIRTY_S	Directory Hit : On Dirty Line in S State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x04	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.DIRTY_P	Directory Hit : On Dirty Line in L State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x08	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.DIRTY_A	Directory Hit : On Dirty Line in A State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x10	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.CLEAN_I	Directory Hit : On NonDirty Line in I State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x20	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.CLEAN_S	Directory Hit : On NonDirty Line in S State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x40	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.CLEAN_P	Directory Hit : On NonDirty Line in L State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1d	0x80	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_HIT.CLEAN_A	Directory Hit : On NonDirty Line in A State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x01	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.DIRTY_I	Directory Miss : On Dirty Line in I State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x02	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.DIRTY_S	Directory Miss : On Dirty Line in S State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x04	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.DIRTY_P	Directory Miss : On Dirty Line in L State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x08	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.DIRTY_A	Directory Miss : On Dirty Line in A State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x10	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.CLEAN_I	Directory Miss : On NonDirty Line in I State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x20	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.CLEAN_S	Directory Miss : On NonDirty Line in S State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x40	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.CLEAN_P	Directory Miss : On NonDirty Line in L State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1e	0x80	0x00	0x00	0x00000000	UNC_M2M_DIRECTORY_MISS.CLEAN_A	Directory Miss : On NonDirty Line in A State	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1F	0x04	0x00	0x00	0x00000000	UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN	Tag Hit : Clean NearMem Underfill Hit	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x1F	0x08	0x00	0x00	0x00000000	UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY	Tag Hit : Dirty NearMem Underfill Hit	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x01	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x01	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x02	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.I2S	Multi-socket cacheline Directory update from I to S	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x02	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x02	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x04	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.I2A	Multi-socket cacheline Directory update from I to A	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x04	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x04	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x08	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.S2I	Multi-socket cacheline Directory update from S to I	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x08	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x08	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x10	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.S2A	Multi-socket cacheline Directory update from S to A	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x10	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x10	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x20	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.A2I	Multi-socket cacheline Directory update from A to I	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x20	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x20	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x40	0x00	0x00	0x03	UNC_M2M_DIRECTORY_UPDATE.A2S	Multi-socket cacheline Directory update from A to S	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x40	0x00	0x00	0x00000001	UNC_M2M_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x21	0x40	0x00	0x00	0x00000002	UNC_M2M_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM	Multi-socket cacheline Directory Updates	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x01	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.NORMAL	UNC_M2M_IMC_READS.NORMAL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x01	0x00000000	0x00000000	0x00000001	UNC_M2M_IMC_READS.CH0_NORMAL	UNC_M2M_IMC_READS.CH0_NORMAL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x01	0x00000000	0x00000000	0x00000002	UNC_M2M_IMC_READS.CH1_NORMAL	UNC_M2M_IMC_READS.CH1_NORMAL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x02	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0_ISOCH	UNC_M2M_IMC_READS.CH0_ISOCH	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x02	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1_ISOCH	UNC_M2M_IMC_READS.CH1_ISOCH	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x02	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.ISOCH	UNC_M2M_IMC_READS.ISOCH	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x04	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.ALL	Reads to iMC issued	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x04	0x00000000	0x00000000	0x00000001	UNC_M2M_IMC_READS.CH0_ALL	UNC_M2M_IMC_READS.CH0_ALL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x04	0x00000000	0x00000000	0x00000002	UNC_M2M_IMC_READS.CH1_ALL	UNC_M2M_IMC_READS.CH1_ALL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0.TO_NM1LM	UNC_M2M_IMC_READS.CH0.TO_NM1LM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1.TO_NM1LM	UNC_M2M_IMC_READS.CH1.TO_NM1LM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.TO_NM1LM	UNC_M2M_IMC_READS.TO_NM1LM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM	UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM	UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x08	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.TO_DDR_AS_MEM	UNC_M2M_IMC_READS.TO_DDR_AS_MEM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0.TO_NMCache	UNC_M2M_IMC_READS.CH0.TO_NMCache	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1.TO_NMCache	UNC_M2M_IMC_READS.CH1.TO_NMCache	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.TO_NMCACHE	UNC_M2M_IMC_READS.TO_NMCACHE	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE	UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE	UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x10	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.TO_DDR_AS_CACHE	UNC_M2M_IMC_READS.TO_DDR_AS_CACHE	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x20	0x00000000	0x00000000	0x00000001	UNC_M2M_IMC_READS.CH0_TO_PMM	UNC_M2M_IMC_READS.CH0_TO_PMM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x20	0x00000000	0x00000000	0x00000002	UNC_M2M_IMC_READS.CH1_TO_PMM	UNC_M2M_IMC_READS.CH1_TO_PMM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x40	0x00	0x00	0x00000001	UNC_M2M_IMC_READS.CH0_FROM_TGR	UNC_M2M_IMC_READS.CH0_FROM_TGR	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x40	0x00	0x00	0x00000002	UNC_M2M_IMC_READS.CH1_FROM_TGR	UNC_M2M_IMC_READS.CH1_FROM_TGR	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x24	0x40	0x00	0x00	0x00000003	UNC_M2M_IMC_READS.FROM_TGR	UNC_M2M_IMC_READS.FROM_TGR	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x0000001a	UNC_M2M_IMC_WRITES.NI	Non-Inclusive - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x0000000a	UNC_M2M_IMC_WRITES.CH0.NI	Non-Inclusive - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000012	UNC_M2M_IMC_WRITES.CH1.NI	Non-Inclusive - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000009	UNC_M2M_IMC_WRITES.CH0_FROM_TGR	From TGR - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x0000000C	UNC_M2M_IMC_WRITES.CH0_NI_MISS	Non-Inclusive Miss - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000011	UNC_M2M_IMC_WRITES.CH1_FROM_TGR	From TGR - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000014	UNC_M2M_IMC_WRITES.CH1_NI_MISS	Non-Inclusive Miss - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000019	UNC_M2M_IMC_WRITES.FROM_TGR	From TGR - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x0000001C	UNC_M2M_IMC_WRITES.NI_MISS	Non-Inclusive Miss - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x0000000a	UNC_M2M_IMC_WRITES.CH0_NI	Non-Inclusive - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x00	0x00	0x00	0x00000012	UNC_M2M_IMC_WRITES.CH1_NI	Non-Inclusive - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x01	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.FULL	Full Non-ISOCH - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x01	0x00000000	0x00000000	0x00000008	UNC_M2M_IMC_WRITES.CH0_FULL	UNC_M2M_IMC_WRITES.CH0_FULL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x01	0x00000000	0x00000000	0x00000010	UNC_M2M_IMC_WRITES.CH1_FULL	Full Line Non-ISOCH - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x02	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.PARTIAL	Partial Non-ISOCH - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x02	0x00000000	0x00000000	0x00000008	UNC_M2M_IMC_WRITES.CH0_PARTIAL	UNC_M2M_IMC_WRITES.CH0_PARTIAL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x02	0x00000000	0x00000000	0x00000010	UNC_M2M_IMC_WRITES.CH1_PARTIAL	Partial Non-ISOCH - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x04	0x00	0x00	0x00000008	UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH	UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x04	0x00	0x00	0x00000010	UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH	ISOCH Full Line - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x04	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.FULL_ISOCH	ISOCH Full Line - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x08	0x00	0x00	0x00000008	UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH	UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x08	0x00	0x00	0x00000010	UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH	ISOCH Partial - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x08	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.PARTIAL_ISOCH	ISOCH Partial - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x10	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.ALL	All Writes - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x10	0x00000000	0x00000000	0x00000008	UNC_M2M_IMC_WRITES.CH0_ALL	UNC_M2M_IMC_WRITES.CH0_ALL	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x10	0x00000000	0x00000000	0x00000010	UNC_M2M_IMC_WRITES.CH1_ALL	All Writes - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x20	0x00	0x00	0x00000008	UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM	UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x20	0x00	0x00	0x00000010	UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM	DDR - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x20	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM	DDR - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x40	0x00	0x00	0x00000008	UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE	DDR, acting as Cache - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x40	0x00	0x00	0x00000010	UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE	DDR, acting as Cache - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x40	0x00	0x00	0x00000018	UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE	DDR, acting as Cache - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x80	0x00000000	0x00000000	0x00000008	UNC_M2M_IMC_WRITES.CH0_TO_PMM	PMM - Ch0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x25	0x80	0x00000000	0x00000000	0x00000010	UNC_M2M_IMC_WRITES.CH1_TO_PMM	PMM - Ch1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x2e	0x00	0x00	0x00	0x00000000	UNC_M2M_TGR_AD_CREDITS	Number AD Ingress Credits	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x2f	0x00	0x00	0x00	0x00000000	UNC_M2M_TGR_BL_CREDITS	Number BL Ingress Credits	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x32	0x04	0x00	0x00	0x00000001	UNC_M2M_TRACKER_INSERTS.CH0	Tracker Inserts : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x32	0x04	0x00	0x00	0x00000002	UNC_M2M_TRACKER_INSERTS.CH1	Tracker Inserts : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x33	0x01	0x00	0x00	0x00000000	UNC_M2M_TRACKER_OCCUPANCY.CH0	Tracker Occupancy : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x33	0x02	0x00	0x00	0x00000000	UNC_M2M_TRACKER_OCCUPANCY.CH1	Tracker Occupancy : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x35	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NE.CH0	Write Tracker Cycles Not Empty : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x35	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NE.CH1	Write Tracker Cycles Not Empty : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x35	0x04	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NE.MIRR	Write Tracker Cycles Not Empty : Mirror	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x35	0x08	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR	Write Tracker Cycles Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x35	0x10	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NE.MIRR_PWR	Write Tracker Cycles Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x37	0x01	0x00	0x00	0x00	UNC_M2M_WPQ_NO_REG_CRD.CHN0	M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x37	0x02	0x00	0x00	0x00	UNC_M2M_WPQ_NO_REG_CRD.CHN1	M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x38	0x01	0x00	0x00	0x00	UNC_M2M_WPQ_NO_SPEC_CRD.CHN0	M2M->iMC WPQ Cycles w/Credits - Special : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x38	0x02	0x00	0x00	0x00	UNC_M2M_WPQ_NO_SPEC_CRD.CHN1	M2M->iMC WPQ Cycles w/Credits - Special : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x40	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_INSERTS.CH0	Write Tracker Inserts : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x40	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_INSERTS.CH1	Write Tracker Inserts : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x42	0x01	0x00	0x00	0x00000000	UNC_M2M_WPQ_FLUSH.CH0	WPQ Flush : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x42	0x02	0x00	0x00	0x00000000	UNC_M2M_WPQ_FLUSH.CH1	WPQ Flush : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x44	0x80	0x00	0x00	0x00000000	UNC_M2M_IGR_STARVE_WINNER.MASK7	Count when Starve Glocab counter is at 7	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x47	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0	Write Tracker Posted Occupancy : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x47	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1	Write Tracker Posted Occupancy : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x48	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0	Write Tracker Posted Inserts : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x48	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1	Write Tracker Posted Inserts : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4a	0x00	0x00	0x00	0x00000000	UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED	Counts the time when FM didn't do d2c for fill reads (cross tile case)	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4b	0x03	0x00	0x00	0x00	UNC_M2M_TAG_MISS	UNC_M2M_TAG_MISS	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4c	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0	Write Tracker Non-Posted Occupancy : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4c	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1	Write Tracker Non-Posted Occupancy : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4d	0x01	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0	Write Tracker Non-Posted Inserts : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x4d	0x02	0x00	0x00	0x00000000	UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1	Write Tracker Non-Posted Inserts : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x54	0x01	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_OCCUPANCY.CH0	Prefetch CAM Occupancy : Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x54	0x02	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_OCCUPANCY.CH1	Prefetch CAM Occupancy : Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x54	0x03	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_OCCUPANCY.ALLCH	Prefetch CAM Occupancy : All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x01	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.CH0_XPT	Prefetch CAM Inserts : XPT - Ch 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x02	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.CH0_UPI	Prefetch CAM Inserts : UPI - Ch 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x04	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.CH1_XPT	Prefetch CAM Inserts : XPT - Ch 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x05	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH	Prefetch CAM Inserts : XPT - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x08	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.CH1_UPI	Prefetch CAM Inserts : UPI - Ch 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x56	0x0a	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH	Prefetch CAM Inserts : UPI - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x01	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT	Data Prefetches Dropped	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x02	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI	Data Prefetches Dropped	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x04	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT	Data Prefetches Dropped	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x05	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH	Data Prefetches Dropped	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x08	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI	Data Prefetches Dropped	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x58	0x0a	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH	Data Prefetches Dropped : UPI - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5c	0x00	0x00	0x00	0x00	UNC_M2M_PREFCAM_CIS_DROPS	UNC_M2M_PREFCAM_CIS_DROPS	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5d	0x05	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH	: XPT - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5d	0x0a	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH	: UPI - All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5E	0x10	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED	Demands Not Merged with CAMed Prefetches	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5E	0x20	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_MERGED	Demands Not Merged with CAMed Prefetches	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5E	0x40	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_DEMAND_NO_MERGE.RD_MERGED	Demands Not Merged with CAMed Prefetches	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5f	0x01	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RESP_MISS.CH0	: Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5f	0x02	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RESP_MISS.CH1	: Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x5F	0x03	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RESP_MISS.ALLCH	All Channels	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x60	0x00	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RxC_OCCUPANCY	AD Ingress (from CMS) Occupancy - Prefetches	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x62	0x01	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED	UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x62	0x02	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED	UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x62	0x04	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT	UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0x62	0x08	0x00	0x00	0x00000000	UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS	UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0xba	0x01	0x00	0x00	0x800000	UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP	Egress Blocking due to Ordering requirements : Up	0,1,2,3	na	0	0	0x00	PGMABLE
M2M	0xba	0x04	0x00	0x00	0x800000	UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN	Egress Blocking due to Ordering requirements : Down	0,1,2,3	na	0	0	0x00	PGMABLE
