# Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.04
# 08/09/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
IMC	0x01	0x01	0x00	0x00	0x00000000	UNC_M_CLOCKTICKS	Number of DRAM DCLK clock cycles while the event is enabled	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x02	0xF7	0x00	0x00	0x00000000	UNC_M_ACT_COUNT.ALL	DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x03	0xF8	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.PGT	DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x03	0xFF	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.ALL	DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xC1	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.RD_REG	CAS count for SubChannel 0 regular reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xC4	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL	CAS count for SubChannel 0 underfill reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xCF	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.RD	CAS count for SubChannel 0, all reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xF0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.WR	CAS count for SubChannel 0, all writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xFF	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.ALL	CAS count for SubChannel 0, all CAS operations	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xC1	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.RD_REG	CAS count for SubChannel 1 regular reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xC4	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL	CAS count for SubChannel 1 underfill reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xCF	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.RD	CAS count for SubChannel 1, all reads	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xF0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.WR	CAS count for SubChannel 1, all writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xFF	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.ALL	CAS count for SubChannel 1, all CAS operations	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0x10	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.SCH0_PCH0	Read Pending Queue inserts for subchannel 0, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0x20	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.SCH0_PCH1	Read Pending Queue inserts for subchannel 0, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0x40	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.SCH1_PCH0	Read Pending Queue inserts for subchannel 1, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0x80	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.SCH1_PCH1	Read Pending Queue inserts for subchannel 1, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x1a	0x00	0x00	0x00	0x00000000	UNC_M_RDB_OCCUPANCY_SCH0	Read buffer occupancy on subchannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x1b	0x00	0x00	0x00	0x00000000	UNC_M_RDB_OCCUPANCY_SCH1	Read buffer occupancy on subchannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0x10	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.SCH0_PCH0	Write Pending Queue inserts for subchannel 0, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0x20	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.SCH0_PCH1	Write Pending Queue inserts for subchannel 0, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0x40	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.SCH1_PCH0	Write Pending Queue inserts for subchannel 1, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0x80	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.SCH1_PCH1	Write Pending Queue inserts for subchannel 1, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x80	0x00	0x00	0x00	0x00000000	UNC_M_RPQ_OCCUPANCY_SCH0_PCH0	Read pending queue occupancy for subchannel 0, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x81	0x00	0x00	0x00	0x00000000	UNC_M_RPQ_OCCUPANCY_SCH0_PCH1	Read pending queue occupancy for subchannel 0, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x82	0x00	0x00	0x00	0x00000000	UNC_M_RPQ_OCCUPANCY_SCH1_PCH0	Read pending queue occupancy for subchannel 1, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x83	0x00	0x00	0x00	0x00000000	UNC_M_RPQ_OCCUPANCY_SCH1_PCH1	Read pending queue occupancy for subchannel 1, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x84	0x00	0x00	0x00	0x00000000	UNC_M_WPQ_OCCUPANCY_SCH0_PCH0	Write pending queue occupancy for subchannel 0, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x85	0x00	0x00	0x00	0x00000000	UNC_M_WPQ_OCCUPANCY_SCH0_PCH1	Write pending queue occupancy for subchannel 0, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x86	0x00	0x00	0x00	0x00000000	UNC_M_WPQ_OCCUPANCY_SCH1_PCH0	Write pending queue occupancy for subchannel 1, pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x87	0x00	0x00	0x00	0x00000000	UNC_M_WPQ_OCCUPANCY_SCH1_PCH1	Write pending queue occupancy for subchannel 1, pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
