# Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.04
# 08/09/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
IMC	0x01	0x00	0x00	0x00	0x00000000	UNC_M_HCLOCKTICKS	Number of DRAM HCLK clock cycles while the event is enabled	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x02	0xF1	0x00	0x00	0x00000000	UNC_M_ACT_COUNT.RD	DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x02	0xF2	0x00	0x00	0x00000000	UNC_M_ACT_COUNT.WR	DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x02	0xF4	0x00	0x00	0x00000000	UNC_M_ACT_COUNT.UFILL	DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x03	0xF1	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.RD	DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x03	0xF2	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.WR	DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x03	0xF4	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.UFILL	DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xD0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.WR_NONPRE	CAS count for SubChannel 0 regular writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x05	0xE0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH0.WR_PRE	CAS count for SubChannel 0 auto-precharge writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xD0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.WR_NONPRE	CAS count for SubChannel 1 regular writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x06	0xE0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT_SCH1.WR_PRE	CAS count for SubChannel 1 auto-precharge writes	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0x50	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.PCH0	Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x10	0xA0	0x00	0x00	0x00000000	UNC_M_RPQ_INSERTS.PCH1	Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x17	0x40	0x00	0x00	0x00000000	UNC_M_RDB_INSERTS.SCH0	Read buffer inserts on subchannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x17	0x80	0x00	0x00	0x00000000	UNC_M_RDB_INSERTS.SCH1	Read buffer inserts on subchannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0x50	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.PCH0	Write Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
IMC	0x22	0xA0	0x00	0x00	0x00000000	UNC_M_WPQ_INSERTS.PCH1	Write Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
