# Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.03
# 08/19/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
UPI LL	0x02	0x01	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT0	Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x02	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT1	Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x04	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT2	Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x08	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.DATA	Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x10	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.LLCRD	Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x20	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.NULL	Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x40	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.LLCTRL	Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x80	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.PROTHDR	Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT0	Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT1	Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT2	Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x08	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.DATA	Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x10	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.LLCRD	Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x20	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.NULL	Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x27	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.ALL_NULL	Null FLITs received from any slot	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x40	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.LLCTRL	Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x47	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.IDLE	Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x80	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.PROTHDR	Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x08	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.REQ	Matches on Transmit path of a UPI Port : Request	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x08	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC	Matches on Transmit path of a UPI Port : Request, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x09	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.SNP	Matches on Transmit path of a UPI Port : Snoop	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x09	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC	Matches on Transmit path of a UPI Port : Snoop, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0A	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA	Matches on Transmit path of a UPI Port : Response - No Data	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0A	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC	Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0C	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA	Matches on Transmit path of a UPI Port : Response - Data	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0C	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC	Matches on Transmit path of a UPI Port : Response - Data, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0D	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.WB	Matches on Transmit path of a UPI Port : Writeback	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0D	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC	Matches on Transmit path of a UPI Port : Writeback, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0E	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB	Matches on Transmit path of a UPI Port : Non-Coherent Bypass	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0E	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0F	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS	Matches on Transmit path of a UPI Port : Non-Coherent Standard	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x0F	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0x2a	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI	Matches on Transmit path of a UPI Port : Response - Invalid	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x04	0xaa	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT	Matches on Transmit path of a UPI Port : Response - Conflict	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x08	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC	Matches on Receive path of a UPI Port : Request, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x09	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.SNP	Matches on Receive path of a UPI Port : Snoop	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x09	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC	Matches on Receive path of a UPI Port : Snoop, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0A	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA	Matches on Receive path of a UPI Port : Response - No Data	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0A	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC	Matches on Receive path of a UPI Port : Response - No Data, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0C	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA	Matches on Receive path of a UPI Port : Response - Data	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0C	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC	Matches on Receive path of a UPI Port : Response - Data, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0D	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC	Matches on Receive path of a UPI Port : Writeback, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0E	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB	Matches on Receive path of a UPI Port : Non-Coherent Bypass	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0E	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0F	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS	Matches on Receive path of a UPI Port : Non-Coherent Standard	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x0F	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0x2a	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI	Matches on Receive path of a UPI Port : Response - Invalid	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x05	0xaa	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT	Matches on Receive path of a UPI Port : Response - Conflict	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x21	0x00	0x00	0x00	0x00000000	UNC_UPI_L1_POWER_CYCLES	Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x27	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES	Cycles in L0p	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x28	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x29	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT0	RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT1	RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT2	RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT0	RxQ Occupancy - All Packets : Slot 0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT1	RxQ Occupancy - All Packets : Slot 1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT2	RxQ Occupancy - All Packets : Slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x40	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL_INSERTS	Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x42	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL_OCCUPANCY	Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.	0,1,2,3	na	0	0	0x00	PGMABLE
