# Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.26
# 04/24/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
UBOX	0x42	0x01	0x00	0x00	0x00	UNC_U_EVENT_MSG.VLW_RCVD	Message Received : VLW	0,1	na	0	0	0x00	PGMABLE
UBOX	0x42	0x02	0x00	0x00	0x00	UNC_U_EVENT_MSG.MSI_RCVD	Message Received : MSI	0,1	na	0	0	0x00	PGMABLE
UBOX	0x42	0x04	0x00	0x00	0x00	UNC_U_EVENT_MSG.IPI_RCVD	Message Received : IPI	0,1	na	0	0	0x00	PGMABLE
UBOX	0x42	0x08	0x00	0x00	0x00	UNC_U_EVENT_MSG.DOORBELL_RCVD	Message Received : Doorbell	0,1	na	0	0	0x00	PGMABLE
UBOX	0x42	0x10	0x00	0x00	0x00	UNC_U_EVENT_MSG.INT_PRIO	Message Received : Interrupt	0,1	na	0	0	0x00	PGMABLE
UBOX	0x44	0x00	0x00	0x00	0x00	UNC_U_LOCK_CYCLES	IDI Lock/SplitLock Cycles	0,1	na	0	0	0x00	PGMABLE
UBOX	0x45	0x01	0x00	0x00	0x00	UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK	Cycles PHOLD Assert to Ack : Assert to ACK	0,1	na	0	0	0x00	PGMABLE
UBOX	0x46	0x00	0x00	0x00	0x00	UNC_U_RACU_REQUESTS	RACU Request	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4C	0x01	0x00	0x00	0x00	UNC_U_RACU_DRNG.RDRAND	UNC_U_RACU_DRNG.RDRAND	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4C	0x02	0x00	0x00	0x00	UNC_U_RACU_DRNG.RDSEED	UNC_U_RACU_DRNG.RDSEED	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4C	0x04	0x00	0x00	0x00	UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY	UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x01	0x00	0x00	0x00	UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB	UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x02	0x00	0x00	0x00	UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS	UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x04	0x00	0x00	0x00	UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB	UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x08	0x00	0x00	0x00	UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS	UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x10	0x00	0x00	0x00	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x20	0x00	0x00	0x00	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x40	0x00	0x00	0x00	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4D	0x80	0x00	0x00	0x00	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS	UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x01	0x00	0x00	0x00	UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL	UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x02	0x00	0x00	0x00	UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL	UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x04	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB	UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x08	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS	UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x10	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x20	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x40	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC	UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4E	0x80	0x00	0x00	0x00	UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL	UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4F	0x01	0x00	0x00	0x00	UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK	UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK	0,1	na	0	0	0x00	PGMABLE
UBOX	0x4F	0x02	0x00	0x00	0x00	UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC	UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC	0,1	na	0	0	0x00	PGMABLE
