# Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.07
# 08/19/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	EQUAL	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	0x00	INST_RETIRED.ANY	Number of instructions retired. Fixed Counter - architectural event	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0	32	0x00
0x00	0x01	0x00	INST_RETIRED.PREC_DIST	Precise instruction retired with PEBS precise-distribution	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	32	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in a halt state.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	NA	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.CORE	Core cycles when the core is not in a halt state.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x00	0x03	0x00	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	NA	0x00
0x00	0x04	0x00	TOPDOWN.SLOTS	TMA slots available for an unhalted logical processor. Fixed counter - architectural event	35	35	10000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x02	0x07	0x00	DEPENDENT_LOADS.ANY	Count number of times a load is depending on another load that had just write back its data or in previous or  2 cycles back. This event supports in-direct dependency through a single uop.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x04	0x00	LD_BLOCKS.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x82	0x00	LD_BLOCKS.STORE_FORWARD	Loads blocked due to overlapping with a preceding store that cannot be forwarded.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x88	0x00	LD_BLOCKS.NO_SR	The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x02	0x00	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x04	0x00	ITLB_MISSES.WALK_COMPLETED_2M_4M	Code miss in all TLB levels causes a page walk that completes. (2M/4M)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x0e	0x00	ITLB_MISSES.WALK_COMPLETED	Code miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x10	0x00	ITLB_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x10	0x00	ITLB_MISSES.WALK_PENDING	Number of page walks outstanding for an outstanding code request in the PMH each cycle.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x11	0x20	0x01	ITLB_MISSES.STLB_HIT	Instruction fetch requests that miss the ITLB and hit the STLB.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x02	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Page walks completed due to a demand data load to a 4K page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x04	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Page walks completed due to a demand data load to a 2M/4M page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x08	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_1G	Page walks completed due to a demand data load to a 1G page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x0e	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED	Load miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x10	0x00	DTLB_LOAD_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a demand load.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x10	0x00	DTLB_LOAD_MISSES.WALK_PENDING	Number of page walks outstanding for a demand load in the PMH each cycle.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x12	0x20	0x03	DTLB_LOAD_MISSES.STLB_HIT	Loads that miss the DTLB and hit the STLB.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x02	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Page walks completed due to a demand data store to a 4K page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x04	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Page walks completed due to a demand data store to a 2M/4M page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x08	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_1G	Page walks completed due to a demand data store to a 1G page.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x0e	0x00	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x10	0x00	DTLB_STORE_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a store.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x10	0x00	DTLB_STORE_MISSES.WALK_PENDING	Number of page walks outstanding for a store in the PMH each cycle.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x20	0x03	DTLB_STORE_MISSES.STLB_HIT	Stores that miss the DTLB and hit the STLB.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x01	0x00	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles where at least 1 outstanding demand data read request is pending.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x01	0x00	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	For every cycle, increments by the number of outstanding demand data read requests pending.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x02	0x00	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD	Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x02	0x00	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x04	0x00	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x04	0x00	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Store Read transactions pending for off-core. Highly correlated.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x08	0x00	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x08	0x00	OFFCORE_REQUESTS_OUTSTANDING.DATA_RD	OFFCORE_REQUESTS_OUTSTANDING.DATA_RD	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x10	0x00	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD	Cycles where data return is pending for a Demand Data Read request who miss L3 cache.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x20	0x10	0x00	OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD	For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x01	0x00	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x02	0x00	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and Non-Cacheable code read requests	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x04	0x00	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x08	0x00	OFFCORE_REQUESTS.DATA_RD	Demand and prefetch data reads	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x10	0x00	OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD	Counts demand data read requests that miss the L3 cache.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x21	0x80	0x00	OFFCORE_REQUESTS.ALL_REQUESTS	Any memory transaction that reached the SQ.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_DATA_RD.L3_MISS	Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).	0,1,2,3	0	100003	0x1a6,0x1a7	0x9E7FA000001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_DATA_RD.DRAM	Counts demand data reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x1E780000001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.STREAMING_WR.ANY_RESPONSE	Counts streaming stores that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10800	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_RFO.L3_MISS	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).	0,1,2,3	0	100003	0x1a6,0x1a7	0x9E7FA000002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.	0,1,2,3	0	100003	0x1a6,0x1a7	0x40001E00001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.	0,1,2,3	0	100003	0x1a6,0x1a7	0x20001E00001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2A,0x2B	0x01	0x00	OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.	0,1,2,3	0	100003	0x1a6,0x1a7	0x40001E00002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0x2c	0x10	0x00	SQ_MISC.BUS_LOCK	Counts bus locks, accounts for cache line split locks and UC locks.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2d	0x01	0x00	XQ.FULL	Cycles the uncore cannot take further requests	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x41	0x00	LONGEST_LAT_CACHE.MISS	Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	0x00	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.CORE_P	Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x01	0x00	CPU_CLK_UNHALTED.REF_TSC_P	Reference cycles when the core is not in halt state.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	NA	0x00
0x40	0x01	0x00	SW_PREFETCH_ACCESS.NTA	Number of PREFETCHNTA instructions executed.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x40	0x02	0x00	SW_PREFETCH_ACCESS.T0	Number of PREFETCHT0 instructions executed.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x40	0x04	0x00	SW_PREFETCH_ACCESS.T1_T2	Number of PREFETCHT1 or PREFETCHT2 instructions executed.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x40	0x08	0x00	SW_PREFETCH_ACCESS.PREFETCHW	Number of PREFETCHW instructions executed.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x40	0x0f	0x00	SW_PREFETCH_ACCESS.ANY	Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x42	0x02	0x00	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x44	0x00	0x04	MEM_STORE_RETIRED.MEMSIDE_CACHE	Number of cache-lines required by retired stores whose Data Source is: Memory Side Cache	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100021	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x44	0x01	0x00	MEM_STORE_RETIRED.L2_HIT	MEM_STORE_RETIRED.L2_HIT	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	200003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x46	0x01	0x00	MEMORY_STALLS.L1	Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x46	0x02	0x00	MEMORY_STALLS.L2	Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x46	0x04	0x00	MEMORY_STALLS.L3	Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x46	0x08	0x00	MEMORY_STALLS.MEM	Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x48	0x01	0x00	L1D_PENDING.LOAD	Number of L1D misses that are outstanding	2	2	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x01	0x00	L1D_MISS.LOAD	Number of demand requests that missed L1D cache	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x02	0x00	L1D_MISS.FB_FULL	Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x04	0x00	L1D_MISS.L2_STALLS	Number of cycles a demand request has waited due to L1D due to lack of L2 resources.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x60	0x01	0x00	BACLEARS.ANY	Clears due to Unknown Branches.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x61	0x02	0x00	DSB2MITE_SWITCHES.PENALTY_CYCLES	DSB-to-MITE switch true penalty cycles.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x01	0x00	INST_DECODED.DECODERS	Instruction decoders utilized in a cycle	2	2	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x76	0x01	0x00	UOPS_DECODED.DEC0_UOPS	Number of non dec-by-all uops decoded by decoder	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x04	0x00	IDQ.MITE_CYCLES_ANY	Cycles MITE is delivering any Uop	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x04	0x00	IDQ.MITE_CYCLES_OK	Cycles MITE is delivering optimal number of Uops	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x04	0x00	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x08	0x00	IDQ.DSB_CYCLES_ANY	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x08	0x00	IDQ.DSB_CYCLES_OK	Cycles DSB is delivering optimal number of Uops	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x08	0x00	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x20	0x00	IDQ.MS_CYCLES_ANY	Cycles when uops are being delivered to IDQ while MS is busy	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x20	0x00	IDQ.MS_SWITCHES	Number of switches from DSB or MITE to the MS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0x79	0x20	0x00	IDQ.MS_UOPS	Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x04	0x00	ICACHE_DATA.STALLS	Cycles where a code fetch is stalled due to L1 instruction cache miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x04	0x00	ICACHE_DATA.STALL_PERIODS	ICACHE_DATA.STALL_PERIODS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0x83	0x04	0x00	ICACHE_TAG.STALLS	Cycles where a code fetch is stalled due to L1 instruction cache tag miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x87	0x01	0x00	DECODE.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x87	0x02	0x00	DECODE.MS_BUSY	Cycles the Microcode Sequencer is busy.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	IDQ_BUBBLES.CORE	This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE	This event is deprecated. [This event is alias to IDQ_BUBBLES.STARVATION_CYCLES]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	NA	0x01
0x9c	0x01	0x00	IDQ_BUBBLES.CYCLES_FE_WAS_OK	Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	IDQ_BUBBLES.STARVATION_CYCLES	Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x04	0x00	IDQ_BUBBLES.FETCH_LATENCY	Cycles when no uops are delivered by the IDQ for 2 or more cycles when backend of the machine is not stalled - normally indicating a Fetch Latency issue	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa2	0x02	0x00	BE_STALLS.SCOREBOARD	Counts cycles where the pipeline is stalled due to serializing operations.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa3	0x04	0x00	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x453	0	0	0	0	0	0	0	0	0	NA	0x00
0xa3	0x10	0x00	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x1053	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x01	0x00	TOPDOWN.SLOTS_P	TMA slots available for an unhalted logical processor. General counter - architectural event	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN.BACKEND_BOUND_SLOTS	This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x04	0x00	TOPDOWN.BAD_SPEC_SLOTS	TMA slots wasted due to incorrect speculations.	0	0	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x08	0x00	TOPDOWN.BR_MISPREDICT_SLOTS	TMA slots wasted due to incorrect speculation by branch mispredictions	0	0	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xa4	0x10	0x00	TOPDOWN.MEMORY_BOUND_SLOTS	TOPDOWN.MEMORY_BOUND_SLOTS	3	3	10000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa5	0x01	0x00	RS.EMPTY_RESOURCE	Cycles when RS was empty and a resource allocation stall is asserted	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa5	0x07	0x00	RS.EMPTY	Cycles when Reservation Station (RS) is empty for the thread.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa5	0x07	0x00	RS.EMPTY_COUNT	Counts end of periods where the Reservation Station (RS) was empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x1D7	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x02	0x00	EXE_ACTIVITY.1_PORTS_UTIL	Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x04	0x00	EXE_ACTIVITY.2_PORTS_UTIL	Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x08	0x00	EXE_ACTIVITY.3_PORTS_UTIL	Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x0c	0x00	EXE_ACTIVITY.2_3_PORTS_UTIL	Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x10	0x00	EXE_ACTIVITY.4_PORTS_UTIL	Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x21	0x00	EXE_ACTIVITY.BOUND_ON_LOADS	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x553	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x40	0x00	EXE_ACTIVITY.BOUND_ON_STORES	Cycles where the Store Buffer was full and no loads caused an execution stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	NA	0x00
0xa6	0x80	0x00	EXE_ACTIVITY.EXE_BOUND_0_PORTS	Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa8	0x01	0x00	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xa8	0x01	0x00	LSD.CYCLES_OK	Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	NA	0x00
0xa8	0x01	0x00	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xad	0x01	0x00	INT_MISC.RECOVERY_CYCLES	Core cycles the allocator was stalled due to recovery from earlier clear event for this thread	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xad	0x01	0x00	INT_MISC.CLEARS_COUNT	Clears speculative count	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0xad	0x10	0x00	INT_MISC.UOP_DROPPING	TMA slots where uops got dropped	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xad	0x40	0x00	INT_MISC.UNKNOWN_BRANCH_CYCLES	Bubble cycles of BAClear (Unknown Branch).	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x3F7	0x7	0	2	1	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xad	0x80	0x00	INT_MISC.CLEAR_RESTEER_CYCLES	Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xae	0x01	0x00	UOPS_ISSUED.ANY	Uops that RAT issues to RS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xae	0x01	0x00	UOPS_ISSUED.CYCLES	UOPS_ISSUED.CYCLES	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xb0	0x01	0x00	ARITH.FPDIV_ACTIVE	Cycles when floating-point divide unit is busy executing divide or square root operations.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xb0	0x08	0x00	ARITH.IDIV_ACTIVE	Cycles when integer divide unit is busy executing divide or square root operations.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xb0	0x09	0x00	ARITH.DIV_ACTIVE	Cycles when divide unit is busy executing divide or square root operations.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.CYCLES_GE_1	Cycles where at least 1 uop was executed per-thread	3	3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.CYCLES_GE_2	Cycles where at least 2 uops were executed per-thread	3	3	2000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.CYCLES_GE_3	Cycles where at least 3 uops were executed per-thread	3	3	2000003	0x00	0x00	0	2	0	0	0x353	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.CYCLES_GE_4	Cycles where at least 4 uops were executed per-thread	3	3	2000003	0x00	0x00	0	2	0	0	0x453	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	3	3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x01	0x00	UOPS_EXECUTED.STALLS	Counts number of cycles no uops were dispatched to be executed on this thread.	3	3	2000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	NA	0x00
0xb1	0x10	0x00	UOPS_EXECUTED.X87	Counts the number of x87 uops dispatched.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x01	0x00	UOPS_DISPATCHED.INT_EU_ALL	Uops executed on any INT EU ports	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x02	0x00	UOPS_DISPATCHED.ALU	Uops executed on INT EU ALU ports.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x04	0x00	UOPS_DISPATCHED.LOAD	Uops executed on Load ports	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x08	0x00	UOPS_DISPATCHED.SLOW	Number of Uops dispatched/executed by Slow EU (e.g. 3+ cycles LEA, >1 cycles shift, iDIVs, CR; *H operation)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x10	0x00	UOPS_DISPATCHED.STD	Uops executed on STD ports	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x20	0X00	UOPS_DISPATCHED.SHIFT	Number of (shift) 1-cycle Uops dispatched/executed by any of the Shift Eus	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x40	0x00	UOPS_DISPATCHED.JMP	Number of Uops dispatched/executed by any of the 3 JEUs (all ups that hold the JEU including macro; micro jumps; fetch-from-eip)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x80	0x00	UOPS_DISPATCHED.STA	Number of Uops dispatched on STA ports	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x01	0x00	FP_ARITH_DISPATCHED.V0	Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD*/SUB*/MUL/FMA*/DPP.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x02	0x00	FP_ARITH_DISPATCHED.V1	Number of FP-arith-uops dispatched on 2nd VEC port (port 1)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x04	0x00	FP_ARITH_DISPATCHED.V2	Number of FP-arith-uops dispatched on 3rd VEC port (port 5)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x08	0x00	FP_ARITH_DISPATCHED.V3	Number of FP-arith-uops dispatched on 4th VEC port	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc0	0x00	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter - architectural event	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	0	0	0x00
0xc0	0x02	0x00	INST_RETIRED.NOP	Retired NOP instructions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x08	0x00	INST_RETIRED.REP_ITERATION	Iterations of Repeat string retired instructions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x10	0x00	INST_RETIRED.BR_FUSED	retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x30	0x00	INST_RETIRED.MACRO_FUSED	INST_RETIRED.MACRO_FUSED	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc1	0x02	0x00	ASSISTS.FP	Counts all microcode FP assists.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc1	0x04	0x00	ASSISTS.HARDWARE	Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc1	0x08	0x00	ASSISTS.PAGE_FAULT	ASSISTS.PAGE_FAULT	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc1	0x10	0x00	ASSISTS.SSE_AVX_MIX	ASSISTS.SSE_AVX_MIX	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc1	0x1f	0x00	ASSISTS.ANY	Number of occurrences where a microcode assist is invoked by hardware.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x01	0x00	UOPS_RETIRED.HEAVY	Retired uops except the last uop of each instruction.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	UOPS_RETIRED.SLOTS	This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	UOPS_RETIRED.STALLS	Cycles without actually retired uops.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	UOPS_RETIRED.CYCLES	Cycles with retired uop(s).	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x04	0x00	UOPS_RETIRED.MS	UOPS_RETIRED.MS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x3F7	0x8	0	2	1	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x04	0x00	UOPS_RETIRED.MS_SWITCHES	Number of non-speculative switches to the Microcode Sequencer (MS)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x3F7	0x8	0	2	1	5	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x01	0x00	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x00	MACHINE_CLEARS.MEMORY_ORDERING	Number of machine clears due to memory ordering conflicts.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	0x00	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	0x00	BR_INST_RETIRED.ALL_BRANCHES	All branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x01	0x01	BR_INST_RETIRED.COND_TAKEN	Taken conditional branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x02	0x00	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x08	0x00	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x10	0x00	BR_INST_RETIRED.COND_NTAKEN	Not taken branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x11	0x01	BR_INST_RETIRED.COND	Conditional branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x20	0x00	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x40	0x00	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc4	0x80	0x00	BR_INST_RETIRED.INDIRECT	Indirect near branch instructions retired (excluding returns)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x00	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x01	0x01	BR_MISP_RETIRED.COND_TAKEN	number of branch instructions retired that were mispredicted and taken.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x02	0x00	BR_MISP_RETIRED.INDIRECT_CALL	Mispredicted indirect CALL retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x08	0x00	BR_MISP_RETIRED.RET	This event counts the number of mispredicted ret instructions retired. Non PEBS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x10	0x00	BR_MISP_RETIRED.COND_NTAKEN	Mispredicted non-taken conditional branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x11	0x01	BR_MISP_RETIRED.COND	Mispredicted conditional branch instructions retired.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x20	0x00	BR_MISP_RETIRED.NEAR_TAKEN	Number of near branch instructions retired that were mispredicted and taken.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x41	0x01	BR_MISP_RETIRED.COND_TAKEN_COST	Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x42	0x00	BR_MISP_RETIRED.INDIRECT_CALL_COST	Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x44	0x00	BR_MISP_RETIRED.ALL_BRANCHES_COST	All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x48	0x00	BR_MISP_RETIRED.RET_COST	Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x50	0x00	BR_MISP_RETIRED.COND_NTAKEN_COST	Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x51	0x01	BR_MISP_RETIRED.COND_COST	Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x60	0x00	BR_MISP_RETIRED.NEAR_TAKEN_COST	Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0x80	0x00	BR_MISP_RETIRED.INDIRECT	Miss-predicted near indirect branch instructions retired (excluding returns)	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc5	0xc0	0x00	BR_MISP_RETIRED.INDIRECT_COST	Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0	0x00
0xc6	0x02	0x00	FRONTEND_RETIRED.MISP_ANT	Mispredicted Retired ANT branches	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x9	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.DSB_MISS	Retired Instructions who experienced a critical DSB miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x11	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.ITLB_MISS	Retired Instructions who experienced iTLB true miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x14	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.L1I_MISS	Retired Instructions who experienced Instruction L1 Cache true miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x12	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.L2_MISS	Retired Instructions who experienced Instruction L2 Cache true miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x13	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_128	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x608006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_16	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x601006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_2	Retired instructions after front-end starvation of at least 2 cycles	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x600206	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1	Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x100206	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_256	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x610006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_32	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x602006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_4	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x600406	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_512	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x620006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_64	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x604006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.LATENCY_GE_8	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x600806	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.STLB_MISS	Retired Instructions who experienced STLB (2nd level TLB) true miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x15	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.UNKNOWN_BRANCH	Retired instructions that caused clears due to being Unknown Branches.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x17	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.MS_FLOWS	Counts flows delivered by the Microcode Sequencer	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x8	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.ANY_DSB_MISS	Retired Instructions who experienced DSB miss.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x1	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	0x00	FRONTEND_RETIRED.ANY_ANT	Retired ANT branches	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100007	0x3F7	0x9	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x01	0x00	FP_ARITH_INST_RETIRED.SCALAR_DOUBLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x01	0x00	FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE	Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x02	0x00	FP_ARITH_INST_RETIRED.SCALAR_SINGLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x02	0x00	FP_ARITH_OPS_RETIRED.SCALAR_SINGLE	Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x03	0x00	FP_ARITH_INST_RETIRED.SCALAR	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x03	0x00	FP_ARITH_OPS_RETIRED.SCALAR	Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x04	0x00	FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x04	0x00	FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE	Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x08	0x00	FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x08	0x00	FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x0C	0x00	FP_ARITH_OPS_RETIRED.VECTOR_128B	FP_ARITH_OPS_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_128B]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x0C	0x00	FP_ARITH_INST_RETIRED.VECTOR_128B	FP_ARITH_INST_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_128B]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x10	0x00	FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x10	0x00	FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE	Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x18	0x00	FP_ARITH_INST_RETIRED.4_FLOPS	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x18	0x00	FP_ARITH_OPS_RETIRED.4_FLOPS	Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x20	0x00	FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x20	0x00	FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE	Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x30	0x00	FP_ARITH_OPS_RETIRED.VECTOR_256B	FP_ARITH_OPS_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_256B]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x30	0x00	FP_ARITH_INST_RETIRED.VECTOR_256B	FP_ARITH_INST_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_256B]	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x3c	0x00	FP_ARITH_INST_RETIRED.VECTOR	This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xc7	0x3c	0x00	FP_ARITH_OPS_RETIRED.VECTOR	Number of any Vector retired FP arithmetic instructions	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	1009	0x3F6	0x80	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	20011	0x3F6	0x10	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	503	0x3F6	0x100	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	100007	0x3F6	0x20	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	100003	0x3F6	0x4	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	101	0x3F6	0x200	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	2003	0x3F6	0x40	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	50021	0x3F6	0x8	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024	Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	53	0x3F6	0x400	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x01	0x00	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048	Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.	2,3,4,5,6,7,8,9	2,3,4,5,6,7,8,9	23	0x3F6	0x800	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xcd	0x02	0x00	MEM_TRANS_RETIRED.STORE_SAMPLE	Retired memory store access operations. A PDist event for PEBS Store Latency Facility.	0,1	0,1	1000003	0x00	0x00	1	2	0	5	0x53	1	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x09	0x00	MEM_INST_RETIRED.STLB_HIT_LOADS	Retired load instructions that hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x0a	0x00	MEM_INST_RETIRED.STLB_HIT_STORES	Retired store instructions that hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0	0x00
0xd0	0x11	0x00	MEM_INST_RETIRED.STLB_MISS_LOADS	Retired load instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x12	0x00	MEM_INST_RETIRED.STLB_MISS_STORES	Retired store instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0	0x00
0xd0	0x21	0x00	MEM_INST_RETIRED.LOCK_LOADS	Retired load instructions with locked access.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x41	0x00	MEM_INST_RETIRED.SPLIT_LOADS	Retired load instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x42	0x00	MEM_INST_RETIRED.SPLIT_STORES	Retired store instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0	0x00
0xd0	0x81	0x00	MEM_INST_RETIRED.ALL_LOADS	Counts all retired load instructions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd0	0x82	0x00	MEM_INST_RETIRED.ALL_STORES	Retired store instructions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0	0x00
0xd0	0x87	0x00	MEM_INST_RETIRED.ANY	All retired memory instructions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0	0x00
0xd1	0x04	0x00	MEM_LOAD_RETIRED.L3_HIT	Retired load instructions with L3 cache hits as data sources	0,1,2,3	0,1,2,3	100021	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd1	0x08	0x00	MEM_LOAD_RETIRED.L1_MISS	Retired load instructions missed L1 cache as data sources	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd1	0x40	0x00	MEM_LOAD_RETIRED.FB_HIT	Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd2	0x01	0x00	MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS	Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd2	0x02	0x00	MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD	Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd2	0x04	0x00	MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM	Retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded.	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd2	0x10	0x00	MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD	Retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$)	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xd3	0x00	0x01	MEM_LOAD_L3_MISS_RETIRED.MEMSIDE_CACHE	Retired load instructions which data source is memory side cache.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0	0x00
0xe0	0x20	0x00	MISC2_RETIRED.LFENCE	LFENCE instructions retired	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	400009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe4	0x01	0x00	MISC_RETIRED.LBR_INSERTS	LBR record is inserted	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0	0x00
0xe5	0x0f	0x00	MEM_UOP_RETIRED.ANY	Retired memory uops for any access	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x03	0x00	INT_VEC_RETIRED.ADD_128	integer ADD, SUB, SAD 128-bit vector instructions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x0c	0x00	INT_VEC_RETIRED.ADD_256	integer ADD, SUB, SAD 256-bit vector instructions.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x10	0x00	INT_VEC_RETIRED.VNNI_128	INT_VEC_RETIRED.VNNI_128	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x13	0x00	INT_VEC_RETIRED.128BIT	Number of vector integer instructions retired of 128-bit vector-width.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x20	0x00	INT_VEC_RETIRED.VNNI_256	INT_VEC_RETIRED.VNNI_256	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x40	0x00	INT_VEC_RETIRED.SHUFFLES	INT_VEC_RETIRED.SHUFFLES	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x80	0x00	INT_VEC_RETIRED.MUL_256	INT_VEC_RETIRED.MUL_256	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0xac	0x00	INT_VEC_RETIRED.256BIT	Number of vector integer instructions retired of 256-bit vector-width.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xec	0x10	0x00	CPU_CLK_UNHALTED.C01	Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xec	0x20	0x00	CPU_CLK_UNHALTED.C02	Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xec	0x40	0x00	CPU_CLK_UNHALTED.PAUSE	Core clocks when a PAUSE is pending.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xec	0x40	0x00	CPU_CLK_UNHALTED.PAUSE_INST	Number of Pause instructions	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x157	0	0	0	0	0	0	0	0	0	NA	0x00
0xec	0x70	0x00	CPU_CLK_UNHALTED.C0_WAIT	Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.	0,1,2,3,4,5,6,7,8,9	0,1,2,3,4,5,6,7,8,9	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
