# Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.07
# 08/19/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	EQUAL	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	0x00	INST_RETIRED.ANY	Fixed Counter: Counts the number of instructions retired.	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0	32	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.CORE	Fixed Counter: Counts the number of unhalted core clock cycles.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.THREAD	Fixed Counter: Counts the number of unhalted core clock cycles.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	NA	0x00
0x00	0x03	0x00	CPU_CLK_UNHALTED.REF_TSC	Fixed Counter: Counts the number of unhalted reference clock cycles.	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	NA	0x00
0x00	0x05	0x00	TOPDOWN_BAD_SPECULATION.ALL	Fixed Counter: Counts the number of issue slots not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	36	36	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x06	0x00	TOPDOWN_FE_BOUND.ALL	Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.	37	37	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x07	0x00	TOPDOWN_RETIRING.ALL	Fixed Counter: Counts the number of consumed retirement slots.	38	38	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x03	0x01	0x00	LD_BLOCKS.DATA_UNKNOWN	Counts the number of occurrences a retired load gets blocked because its address exactly matches an older store whose data is not ready (a.k.a. unknown).  unready_fwd	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x02	0x00	LD_BLOCKS.STORE_FORWARD	Counts the number of occurrences a retired load gets blocked because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forward	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x04	0x00	LD_BLOCKS.ADDRESS_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x08	0x00	LD_BLOCKS.DTLB_MISS	Counts the number of occurrences a load gets blocked because of a micro TLB miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x03	0x10	0x00	LD_BLOCKS.ALL	Counts the number of occurrences a retired load was blocked for any of the following reasons:  utlb_miss, 4k_alias, unknown_sta/bad_fwd, unready_fwd (includes md blocks and esp consuming load blocks)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x01	0x00	MEM_SCHEDULER_BLOCK.ST_BUF	Counts the number of cycles that uops are blocked due to store buffer full	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x02	0x00	MEM_SCHEDULER_BLOCK.LD_BUF	Counts the number of cycles that uops are blocked due to load buffer full	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x04	0x00	MEM_SCHEDULER_BLOCK.RSV	Counts the number of cycles that uops are blocked due to RSV full	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x07	0x00	MEM_SCHEDULER_BLOCK.ALL	Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x01	0x00	LD_HEAD.L1_MISS	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x02	0x00	LD_HEAD.WCB_FULL	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x04	0x00	LD_HEAD.ST_ADDR	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x08	0x00	LD_HEAD.ST_DATA	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to store data forward block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x10	0x00	LD_HEAD.DTLB_MISS	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x20	0x00	LD_HEAD.PGWALK	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x40	0x00	LD_HEAD.OTHER	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x7f	0x00	LD_HEAD.ANY	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x81	0x00	LD_HEAD.L1_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x82	0x00	LD_HEAD.WCB_FULL_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x84	0x00	LD_HEAD.ST_ADDR_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x90	0x00	LD_HEAD.DTLB_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xa0	0x00	LD_HEAD.PGWALK_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xc0	0x00	LD_HEAD.OTHER_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xf4	0x00	LD_HEAD.L1_BOUND_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xff	0x00	LD_HEAD.ANY_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x01	0x00	DTLB_LOAD_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x02	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to load DTLB misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x04	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x0e	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x10	0x00	DTLB_LOAD_MISSES.WALK_PENDING	Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x20	0x00	DTLB_LOAD_MISSES.STLB_HIT_4K	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for 4k page size only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x40	0x00	DTLB_LOAD_MISSES.STLB_HIT_LGPG	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for large page sizes only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x60	0x00	DTLB_LOAD_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x80	0x00	DTLB_LOAD_MISSES.PDE_CACHE_MISS	Counts walks that miss the PDE_CACHE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x0e	0x00	0x00	UOPS_ISSUED.ANY	When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x02	0x00	MISALIGN_MEM_REF.LOAD_PAGE_SPLIT	Counts misaligned loads that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x04	0x00	MISALIGN_MEM_REF.STORE_PAGE_SPLIT	Counts misaligned stores that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x24	0x01	0x00	L2_REQUEST.MISS	Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x24	0x02	0x00	L2_REQUEST.HIT	Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x24	0x04	0x00	L2_REQUEST.REJECTS	Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any), per core event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x24	0x07	0x00	L2_REQUEST.ALL	Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x01	0x00	L2_LINES_IN.I	Counts the number of cache lines filled into the L2 cache that are in Invalid state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x02	0x00	L2_LINES_IN.S	Counts the number of cache lines filled into the L2 cache that are in Shared state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x04	0x00	L2_LINES_IN.E	Counts the number of cache lines filled into the L2 cache that are in Exclusive state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x08	0x00	L2_LINES_IN.M	Counts the number of cache lines filled into the L2 cache that are in Modified state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x10	0x00	L2_LINES_IN.F	Counts the number of cache lines filled into the L2 cache that are in Forward state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x26	0x01	0x00	L2_LINES_OUT.SILENT	Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x26	0x02	0x00	L2_LINES_OUT.NON_SILENT	Counts the number of L2 cache lines that are evicted due to an L2 cache fill	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x26	0x04	0x00	L2_LINES_OUT.USELESS_HWPF	Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x28	0x01	0x00	L2_PREFETCHES_THROTTLED.DPT	Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were  throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor.  Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x28	0x02	0x00	L2_PREFETCHES_THROTTLED.DTP	Counts the number of L2 prefetches initiated by the L2 Stream that were throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x28	0x04	0x00	L2_PREFETCHES_THROTTLED.DTP_OVERRIDE	Counts the number of L2 prefetches initiated by the L2 Stream and not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism besides DTP. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x28	0x08	0x00	L2_PREFETCHES_THROTTLED.XQ_THRESH	Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x29	0x01	0x00	LLC_PREFETCHES_THROTTLED.DPT	Counts the number of LLC prefetches that were  throttled due to Dynamic Prefetch Throttling.  The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x29	0x02	0x00	LLC_PREFETCHES_THROTTLED.DTP	Counts the number of LLC prefetches throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x29	0x04	0x00	LLC_PREFETCHES_THROTTLED.DTP_OVERRIDE	Counts the number of LLC prefetches not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x29	0x08	0x00	LLC_PREFETCHES_THROTTLED.XQ_THRESH	Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x29	0x10	0x00	LLC_PREFETCHES_THROTTLED.HIT_RATE	Counts the number of LLC prefetches throttled due to LLC hit rate in <insert knob name here>. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x41	0x00	LONGEST_LAT_CACHE.MISS	Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	0x00	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x30	0x00	0x00	L2_REJECT_XQ.ANY	Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x31	0x00	0x00	CORE_REJECT_L2Q.ANY	Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x32	0x01	0x00	DYNAMIC_PREFETCH_THROTTLER.LEVEL0_SOC	Counts the number of cycles the L2 Prefetchers are at throttle level 0	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x32	0x02	0x00	DYNAMIC_PREFETCH_THROTTLER.LEVEL1_SOC	Counts the number of cycles the L2 Prefetcher throttle level is at 1	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x32	0x04	0x00	DYNAMIC_PREFETCH_THROTTLER.LEVEL2_SOC	Counts the number of cycles the L2 Prefetcher throttle level is at 2	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x32	0x08	0x00	DYNAMIC_PREFETCH_THROTTLER.LEVEL3_SOC	Counts the number of cycles the L2 Prefetcher throttle level is at 3	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x32	0x10	0x00	DYNAMIC_PREFETCH_THROTTLER.LEVEL4_SOC	Counts the number of cycles the L2 Prefetcher throttle level is at 4	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x01	0x00	MEM_BOUND_STALLS_LOAD.L2_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x78	0x00	MEM_BOUND_STALLS_LOAD.LLC_MISS	Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x7e	0x00	MEM_BOUND_STALLS_LOAD.L2_MISS	Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x7f	0x00	MEM_BOUND_STALLS_LOAD.ALL	Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x80	0x00	MEM_BOUND_STALLS_LOAD.SBFULL	Counts the number of unhalted cycles when the core is stalled to a store buffer full condition	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x35	0x01	0x00	MEM_BOUND_STALLS_IFETCH.L2_HIT	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x35	0x7e	0x00	MEM_BOUND_STALLS_IFETCH.L2_MISS	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x35	0x7f	0x00	MEM_BOUND_STALLS_IFETCH.ALL	Counts the number of cycles the core is stalled due to an instruction cache or TLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.THREAD_P	Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x01	0x00	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	NA	0x00
0x49	0x01	0x00	DTLB_STORE_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a store that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x02	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to store DTLB misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x04	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x0e	0x00	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x10	0x00	DTLB_STORE_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x60	0x00	DTLB_STORE_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x80	0x00	DTLB_STORE_MISSES.PDE_CACHE_MISS	Counts walks that miss the PDE_CACHE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x4c	0x02	0x00	LOAD_HIT_PREFETCH.HW_PF	Counts the number of demand loads that match on a wcb (request buffer) allocated by an L1 hardware prefetch	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x51	0x01	0x00	DL1.DIRTY_EVICTION	Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x63	0x01	0x00	BUS_LOCK.BLOCKED_CYCLES	Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x63	0x02	0x00	BUS_LOCK.LOCK_CYCLES	Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x63	0x04	0x00	BUS_LOCK.NON_SPLIT_LOCKS	Counts the number of non-split locks such as UC locks issued by a Core (does not include cache locks)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x63	0x08	0x00	BUS_LOCK.SPLIT_LOCKS	Counts the number of split locks issued by a Core	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x00	0x00	TOPDOWN_FE_BOUND.ALL_NON_ARCH	Counts the number of retirement slots not consumed due to front end stalls	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x01	0x00	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to ms	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x02	0x00	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x04	0x00	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x08	0x00	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	0x00	TOPDOWN_FE_BOUND.ITLB_MISS	Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x20	0x00	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x40	0x00	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x72	0x00	TOPDOWN_FE_BOUND.FRONTEND_LATENCY	Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x80	0x00	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x8d	0x00	TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH	Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x72	0x00	0x00	TOPDOWN_RETIRING.ALL_NON_ARCH	Counts the number of consumed retirement slots.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x00	0x00	TOPDOWN_BAD_SPECULATION.ALL_P	Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x01	0x00	TOPDOWN_BAD_SPECULATION.NUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x02	0x00	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as  Memory Ordering Machine clears and MRN nukes	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x03	0x00	TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS	Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x04	0x00	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x00	0x00	TOPDOWN_BE_BOUND.ALL_NON_ARCH	Counts the number of retirement slots not consumed due to backend stalls	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x01	0x00	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x02	0x00	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop).  This could be caused by RSV full or load/store buffer block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x08	0x00	TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x10	0x00	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x20	0x00	TOPDOWN_BE_BOUND.REGISTER	Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall.  A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x40	0x00	TOPDOWN_BE_BOUND.REORDER_BUFFER	Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x02	0x00	SERIALIZATION.NON_C01_MS_SCB	Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x04	0x00	SERIALIZATION.C01_MS_SCB	Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x08	0x00	SERIALIZATION.COLOR_STALLS	Counts the number issue slots not consumed  due to a  color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x01	0x00	ICACHE.HIT	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x02	0x00	ICACHE.MISSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x03	0x00	ICACHE.ACCESSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x81	0x04	0x00	ITLB.FILLS	Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x01	0x00	ITLB_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x02	0x00	ITLB_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to instruction fetch misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x04	0x00	ITLB_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x0e	0x00	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x10	0x00	ITLB_MISSES.WALK_PENDING	Counts the number of page walks outstanding for iside in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x20	0x00	ITLB_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x80	0x00	ITLB_MISSES.PDE_CACHE_MISS	Counts walks that miss the PDE_CACHE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	TOPDOWN_FE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to front end stalls	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL	Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x01	0x00	FP_VINT_UOPS_EXECUTED.STD	Counts the number of uops executed on floating point and vector integer store data port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x02	0x00	FP_VINT_UOPS_EXECUTED.P0	Counts the number of uops executed on floating point and vector integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x04	0x00	FP_VINT_UOPS_EXECUTED.P1	Counts the number of uops executed on floating point and vector integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x08	0x00	FP_VINT_UOPS_EXECUTED.P2	Counts the number of uops executed on floating point and vector integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x10	0x00	FP_VINT_UOPS_EXECUTED.P3	Counts the number of uops executed on floating point and vector integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1e	0x00	FP_VINT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1f	0x00	FP_VINT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all floating point ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x01	0x00	INT_UOPS_EXECUTED.LD	Counts the number of uops executed on a load port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x02	0x00	INT_UOPS_EXECUTED.STA	Counts the number of uops executed on a Store address port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x04	0x00	INT_UOPS_EXECUTED.STD_JMP	Counts the number of uops executed on an integer store data and jump port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x08	0x00	INT_UOPS_EXECUTED.P0	Counts the number of uops executed on integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x10	0x00	INT_UOPS_EXECUTED.P1	Counts the number of uops executed on integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x20	0x00	INT_UOPS_EXECUTED.P2	Counts the number of uops executed on integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x40	0x00	INT_UOPS_EXECUTED.P3	Counts the number of uops executed on integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x78	0x00	INT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on integer port  0,1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0xff	0x00	INT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all Integer ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any type of response.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.STREAMING_WR.ANY_RESPONSE	Counts streaming stores that have any type of response.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x10800	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.DRAM	Counts demand data reads that were supplied by DRAM.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x1FBC000001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.L3_MISS	Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x13FBFC00001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_RFO.L3_MISS	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x13FBFC00002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xbc	0x01	0x00	PAGE_WALKER_LOADS.DTLB_L1_HIT	Counts the number of PMH walks that hit in the L1 or WCBs	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xbc	0x02	0x00	PAGE_WALKER_LOADS.DTLB_L2_HIT	Counts the number of PMH walks that hit in the L2	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xbd	0x20	0x00	TLB_FLUSHES.STLB_ANY	Count number of any STLB flush attempts (Entire, PCID, InvPage, CR3 write, etc)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc0	0x00	0x00	INST_RETIRED.ANY_P	Counts the number of instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0xc2	0x00	0x00	UOPS_RETIRED.ALL	Counts the number of uops retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x01	0x00	UOPS_RETIRED.MS	Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	TOPDOWN_RETIRING.ALL_P	Counts the number of consumed retirement slots.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x04	0x00	UOPS_RETIRED.LSD	Counts the number of uops retired that were delivered by the loop stream detector (LSD).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x08	0x00	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x10	0x00	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x20	0x00	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in ms flows	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x00	0x00	MACHINE_CLEARS.ANY	Counts all machine clears for any reason including, but not limited to memory ordering, SMC, and FP assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x00	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of memory ordering machine clears triggered due to a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	0x00	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	0x00	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of memory ordering machine clears triggered due to an internal load passing an older store within the same CPU.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x10	0x00	MACHINE_CLEARS.MRN_NUKE	Counts the number of nukes due to memory renaming	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x20	0x00	MACHINE_CLEARS.PAGE_FAULT	Counts the number of times that the machine clears due to a page fault.  Covers both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x6e	0x00	MACHINE_CLEARS.SLOW	Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x82	0x00	MACHINE_CLEARS.MEMORY_ORDERING_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x88	0x00	MACHINE_CLEARS.DISAMBIGUATION_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x90	0x00	MACHINE_CLEARS.MRN_NUKE_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0xff	0x00	MACHINE_CLEARS.ANY_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	20003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0x7e	0x00	BR_INST_RETIRED.COND	Counts retired JCC (Jump on Conditional Code) branch instructions retired includes both taken and not taken branches	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0x7f	0x00	BR_INST_RETIRED.COND_NTAKEN	Counts the number of not taken JCC branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xbf	0x00	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xc0	0x00	BR_INST_RETIRED.NEAR_TAKEN	Counts the number of taken branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xeb	0x00	BR_INST_RETIRED.INDIRECT	Counts the number of near indirect JMP and near indirect CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xef	0x00	BR_INST_RETIRED.INDIRECT_JMP	Counts the number of near indirect JMP branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xf7	0x00	BR_INST_RETIRED.NEAR_RETURN	Counts the number of near RET branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xf9	0x00	BR_INST_RETIRED.NEAR_CALL	Counts the number of near CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfb	0x00	BR_INST_RETIRED.INDIRECT_CALL	Counts the number of near indirect CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfd	0x00	BR_INST_RETIRED.REL_CALL	Counts the number of near relative CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc4	0xfe	0x00	BR_INST_RETIRED.COND_TAKEN	Counts the number of taken JCC branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x00	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x7e	0x00	BR_MISP_RETIRED.COND	Counts the number of mispredicted JCC branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x7f	0x00	BR_MISP_RETIRED.COND_NTAKEN	Counts the number of mispredicted not taken JCC branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0x80	0x00	BR_MISP_RETIRED.NEAR_TAKEN	Counts the number of mispredicted near taken branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xeb	0x00	BR_MISP_RETIRED.INDIRECT	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xef	0x00	BR_MISP_RETIRED.INDIRECT_JMP	Counts the number of mispredicted near indirect JMP branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xf7	0x00	BR_MISP_RETIRED.RETURN	Counts the number of mispredicted near RET branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xfb	0x00	BR_MISP_RETIRED.INDIRECT_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc5	0xfe	0x00	BR_MISP_RETIRED.COND_TAKEN	Counts the number of mispredicted taken JCC branch instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	NA	0x00
0xc6	0x00	0x00	FRONTEND_RETIRED.ALL	Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x01	0x00	FRONTEND_RETIRED.CISC	Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x02	0x00	FRONTEND_RETIRED.BRANCH_DETECT	Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x04	0x00	FRONTEND_RETIRED.PREDECODE	Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x08	0x00	FRONTEND_RETIRED.DECODE	Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 4 uops	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x10	0x00	FRONTEND_RETIRED.ITLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x20	0x00	FRONTEND_RETIRED.ICACHE	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x40	0x00	FRONTEND_RETIRED.BRANCH_RESTEER	Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc6	0x80	0x00	FRONTEND_RETIRED.OTHER	Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x01	0x00	FP_INST_RETIRED.32B_SP	Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x02	0x00	FP_INST_RETIRED.64B_DP	Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x04	0x00	FP_INST_RETIRED.128B_SP	Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x08	0x00	FP_INST_RETIRED.128B_DP	Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x10	0x00	FP_INST_RETIRED.256B_SP	Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x20	0x00	FP_INST_RETIRED.256B_DP	Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x3f	0x00	FP_INST_RETIRED.ALL	Counts the total number of  floating point retired instructions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x01	0x00	FP_FLOPS_RETIRED.FP64	Counts the number of floating point operations that produce 64 bit double precision results	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x02	0x00	FP_FLOPS_RETIRED.FP32	Counts the number of floating point operations that produce 32 bit single precision results	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x03	0x00	FP_FLOPS_RETIRED.ALL	Counts the number of all types of floating point operations per uop with all default weighting	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc9	0x01	0x00	FRONTEND_RETIRED_SOURCE.ICACHE_L2_HIT	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc9	0x10	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc9	0x20	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x01	0x00	ARITH.IDIV_OCCUPANCY	Counts the number of active integer dividers per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x01	0x00	ARITH.IDIV_ACTIVE	Counts the number of cycles when any of the integer dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x02	0x00	ARITH.FPDIV_OCCUPANCY	Counts the number of active floating point dividers per cycle in the loop stage.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x02	0x00	ARITH.FPDIV_ACTIVE	Counts the number of cycles when any of the floating point dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x03	0x00	ARITH.DIV_ACTIVE	Counts the number of cycles when any of the floating point or integer dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x03	0x00	ARITH.DIV_OCCUPANCY	Counts the number of active floating point and integer dividers per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x04	0x00	ARITH.IDIV_UOPS	Counts the number of integer divider uops executed per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x08	0x00	ARITH.FPDIV_UOPS	Counts the number of floating point divider uops executed per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x0c	0x00	ARITH.DIV_UOPS	Counts the number of floating point and integer divider uops executed per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x8	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x40	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x200	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x4	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x20	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x100	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x10	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x3F6	0x80	0	2	1	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x06	0x00	MEM_UOPS_RETIRED.STORE_LATENCY	Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	1	0	0	1	1	0	0	0	0	NA	0x00
0xd0	0x09	0x00	MEM_UOPS_RETIRED.MRN_LOADS	Counts the number of memory renamed load uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x0a	0x00	MEM_UOPS_RETIRED.MRN_STORES	Counts the number of memory renamed store uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x11	0x00	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Counts the number of load ops retired that filled the STLB - includes those in DTLB_LOAD_MISSES submasks	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x12	0x00	MEM_UOPS_RETIRED.STLB_MISS_STORES	Counts the number of store ops retired (store STLB miss)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x13	0x00	MEM_UOPS_RETIRED.STLB_MISS	Counts the number of memory uops retired that missed in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x21	0x00	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x41	0x00	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x42	0x00	MEM_UOPS_RETIRED.SPLIT_STORES	Counts the number of retired split store uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x43	0x00	MEM_UOPS_RETIRED.SPLIT	Counts the number of memory uops retired that were splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x81	0x00	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x82	0x00	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd0	0x83	0x00	MEM_UOPS_RETIRED.ALL	Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xd1	0x01	0x00	MEM_LOAD_UOPS_RETIRED.L1_HIT	Counts the number of load ops retired that hit the L1 data cache	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x02	0x00	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load ops retired that hit in the L2 cache	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x20	0x00	MEM_LOAD_UOPS_RETIRED.WCB_HIT	Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x40	0x00	MEM_LOAD_UOPS_RETIRED.L1_MISS	Counts the number of load ops retired that miss in the L1 data cache	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd1	0x80	0x00	MEM_LOAD_UOPS_RETIRED.L2_MISS	Counts the number of load ops retired that miss in the L2 cache	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd3	0x01	0x00	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xd3	0x01	0x00	MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	Counts the number of load ops retired that miss the L2 cache, missed the Memory Side Cache and hit in DRAM	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd3	0x40	0x00	MEM_LOAD_UOPS_L3_MISS_RETIRED.MEMSIDE_CACHE	This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.MEMSIDE_CACHE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x01
0xd3	0x40	0x00	MEM_LOAD_UOPS_LLC_MISS_RETIRED.MEMSIDE_CACHE	Counts the number of load ops retired that miss the LLC cache and hit in the Memory Side Cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe0	0x00	0x00	MISC_RETIRED1.WRMSR	Count the number of WRMSR instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe0	0x01	0x00	MISC_RETIRED1.RDPMC_RDTSC_P	Counts the number of RDPMC, RDTSC, and RDTSCP instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe0	0x02	0x00	MISC_RETIRED1.LFENCE	Counts the number of LFENCE instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe0	0xff	0x00	MISC_RETIRED1.CL_INST	Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x00	0x00	MISC_RETIRED2.FAULT_ALL	Counts the number of faults and software interrupts with vector < 32.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x01	0x00	MISC_RETIRED2.VM_EXIT	Counts the number of VM exits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x02	0x00	MISC_RETIRED2.INTEL_PT_CLEARS	Counts the number of PSB+ nuke events and ToPA trap events.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x08	0x00	MISC_RETIRED2.ULI_DELIVERY	Counts the number of user interrupts delivered.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x09	0x00	MISC_RETIRED2.ULI_SENDUIPI	Counts the number of SENDUIPI instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x10	0x00	MISC_RETIRED2.KEYLOCKER_ACCESS	Counts the number of accesses to KeyLocker cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe1	0x11	0x00	MISC_RETIRED2.KEYLOCKER_MISS	Counts the number of misses to KeyLocker cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe4	0x01	0x00	MISC_RETIRED.LBR_INSERTS	Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x01	0x00	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x02	0x00	BACLEARS.INDIRECT	Counts the number of BACLEARS due to an indirect branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x04	0x00	BACLEARS.UNCOND	Counts the number of BACLEARS due to a direct, unconditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x08	0x00	BACLEARS.RETURN	Counts the number of BACLEARS due to a return branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x10	0x00	BACLEARS.COND	Counts the number of BACLEARS due to a conditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x01	0x00	MS_DECODED.MS_ENTRY	Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x02	0x00	MS_DECODED.NANO_CODE	Counts the number of times nanocode flow is executed.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x04	0x00	MS_DECODED.MS_BUSY	Counts the number of cycles that the micro-sequencer is busy.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe8	0x00	0x00	BTCLEAR.ANY	Counts the total number of BTCLEARS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe9	0x01	0x00	DECODE_RESTRICTION.PREDECODE_WRONG	Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xf4	0x00	0x00	XQ_PROMOTION.ALL	Counts the number of prefetch requests that were promoted in the XQ to a demand request.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xf4	0x01	0x00	XQ_PROMOTION.DRDS	Counts the number of prefetch requests that were promoted in the XQ to a demand read.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xf4	0x02	0x00	XQ_PROMOTION.RFOS	Counts the number of prefetch requests that were promoted in the XQ to a demand RFO.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xf4	0x04	0x00	XQ_PROMOTION.CRDS	Counts the number of prefetch requests that were promoted in the XQ to a demand code read.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
