# Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.11
# 08/19/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	NAME	DESCRIPTION	COUNTER	EVENT_STATUS	COUNTER_TYPE
iMC	0x00	0x00	UNC_MC0_TOTAL_REQCOUNT_FREERUN	Counts every read and write request entering the Memory Controller 0.	2	0x00	FREERUN
iMC	0x00	0x00	UNC_MC1_TOTAL_REQCOUNT_FREERUN	Counts every read and write request entering the Memory Controller 1.	5	0x00	FREERUN
iMC	0x00	0x00	UNC_MC0_RDCAS_COUNT_FREERUN	Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).	0	0x00	FREERUN
iMC	0x00	0x00	UNC_MC1_RDCAS_COUNT_FREERUN	Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).	3	0x00	FREERUN
iMC	0x00	0x00	UNC_MC0_WRCAS_COUNT_FREERUN	Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).	1	0x00	FREERUN
iMC	0x00	0x00	UNC_MC1_WRCAS_COUNT_FREERUN	Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).	4	0x00	FREERUN
iMC	0x22	0x00	UNC_M_CAS_COUNT_RD	Read CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x23	0x00	UNC_M_CAS_COUNT_WR	Write CAS command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x24	0x00	UNC_M_ACT_COUNT_RD	ACT command for a read request sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x25	0x00	UNC_M_ACT_COUNT_WR	ACT command for a write request sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x26	0x00	UNC_M_ACT_COUNT_TOTAL	ACT command sent to DRAM	0,1,2,3,4	0x00	PGMABLE
iMC	0x27	0x00	UNC_M_PRE_COUNT_PAGE_MISS	PRE command sent to DRAM for a read/write request	0,1,2,3,4	0x00	PGMABLE
iMC	0x28	0x00	UNC_M_PRE_COUNT_IDLE	PRE command sent to DRAM due to page table idle timer expiration	0,1,2,3,4	0x00	PGMABLE
iMC	0x3A	0x00	UNC_M_RD_DATA	Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.	0,1,2,3,4	0x00	PGMABLE
iMC	0x3B	0x00	UNC_M_WR_DATA	Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.	0,1,2,3,4	0x00	PGMABLE
iMC	0x3C	0x00	UNC_M_TOTAL_DATA	Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.	0,1,2,3,4	0x00	PGMABLE
