# Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.11
# 08/19/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
CODE	UMASK	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	INST_RETIRED.ANY	Number of instructions retired. Fixed Counter - architectural event	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	32	0x00
0x00	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired with PEBS precise-distribution	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	32	0x00
0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	0x00
0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	0x00
0x00	0x04	TOPDOWN.SLOTS	TMA slots available for an unhalted logical processor. Fixed counter - architectural event	35	35	10000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	0x00
0x03	0x04	LD_BLOCKS.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x03	0x82	LD_BLOCKS.STORE_FORWARD	Loads blocked due to overlapping with a preceding store that cannot be forwarded.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x03	0x88	LD_BLOCKS.NO_SR	The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x11	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x11	0x04	ITLB_MISSES.WALK_COMPLETED_2M_4M	Code miss in all TLB levels causes a page walk that completes. (2M/4M)	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x11	0x0e	ITLB_MISSES.WALK_COMPLETED	Code miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x11	0x10	ITLB_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x11	0x10	ITLB_MISSES.WALK_PENDING	Number of page walks outstanding for an outstanding code request in the PMH each cycle.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x11	0x20	ITLB_MISSES.STLB_HIT	Instruction fetch requests that miss the ITLB and hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Page walks completed due to a demand data load to a 4K page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x04	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Page walks completed due to a demand data load to a 2M/4M page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x08	DTLB_LOAD_MISSES.WALK_COMPLETED_1G	Page walks completed due to a demand data load to a 1G page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Load miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x10	DTLB_LOAD_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a demand load.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x12	0x10	DTLB_LOAD_MISSES.WALK_PENDING	Number of page walks outstanding for a demand load in the PMH each cycle.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x12	0x20	DTLB_LOAD_MISSES.STLB_HIT	Loads that miss the DTLB and hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Page walks completed due to a demand data store to a 4K page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x04	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Page walks completed due to a demand data store to a 2M/4M page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x08	DTLB_STORE_MISSES.WALK_COMPLETED_1G	Page walks completed due to a demand data store to a 1G page.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x10	DTLB_STORE_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a store.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x13	0x10	DTLB_STORE_MISSES.WALK_PENDING	Number of page walks outstanding for a store in the PMH each cycle.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x13	0x20	DTLB_STORE_MISSES.STLB_HIT	Stores that miss the DTLB and hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x20	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles where at least 1 outstanding demand data read request is pending.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x20	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	For every cycle, increments by the number of outstanding demand data read requests pending.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x20	0x02	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD	Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x20	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x20	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x20	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Store Read transactions pending for off-core. Highly correlated.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x20	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x20	0x08	OFFCORE_REQUESTS_OUTSTANDING.DATA_RD	OFFCORE_REQUESTS_OUTSTANDING.DATA_RD	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x20	0x10	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD	Cycles where data return is pending for a Demand Data Read request who miss L3 cache.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x20	0x10	OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD	For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and Non-Cacheable code read requests	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x08	OFFCORE_REQUESTS.DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x10	OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD	Counts demand data read requests that miss the L3 cache.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x21	0x80	OFFCORE_REQUESTS.ALL_REQUESTS	Any memory transaction that reached the SQ.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x23	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x28	L2_RQSTS.SWPF_MISS	SW prefetch requests that miss L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x30	L2_RQSTS.HWPF_MISS	L2_RQSTS.HWPF_MISS	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x3f	L2_RQSTS.MISS	Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0x3f	L2_REQUEST.MISS	Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xc1	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xc2	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xc4	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xc8	L2_RQSTS.SWPF_HIT	SW prefetch requests that hit L2 cache.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xdf	L2_RQSTS.HIT	All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xdf	L2_REQUEST.HIT	All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xe1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read access L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xe2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xe4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xf0	L2_RQSTS.ALL_HWPF	L2_RQSTS.ALL_HWPF	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xff	L2_RQSTS.REFERENCES	All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x24	0xff	L2_REQUEST.ALL	All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x25	0x1f	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x26	0x01	L2_LINES_OUT.SILENT	Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x26	0x02	L2_LINES_OUT.NON_SILENT	Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x26	0x04	L2_LINES_OUT.USELESS_HWPF	Cache lines that have been L2 hardware prefetched but not used by demand accesses	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_DATA_RD.L3_MISS	Counts demand data reads that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3FBFC00001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_DATA_RD.DRAM	Counts demand data reads that were supplied by DRAM.	0,1,2,3	0	100003	0x1a6,0x1a7	0x184000001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.STREAMING_WR.ANY_RESPONSE	Counts streaming stores that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10800	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_RFO.L3_MISS	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3	0	100003	0x1a6,0x1a7	0x3FBFC00002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD	Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.	0,1,2,3	0	100003	0x1a6,0x1a7	0x8003C0001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2A,0x2B	0x01	OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.	0,1,2,3	0	100003	0x1a6,0x1a7	0x10003C0002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0x00
0x2c	0x10	SQ_MISC.BUS_LOCK	Counts bus locks, accounts for cache line split locks and UC locks.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x2d	0x01	XQ.FULL_CYCLES	Cycles the uncore cannot take further requests	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	5	0x153	0	0	0	0	0	0	0	0	0	0x00
0x2e	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x2e	0x4f	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	0x00
0x3c	0x01	CPU_CLK_UNHALTED.REF_TSC_P	Reference cycles when the core is not in halt state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	0x00
0x3c	0x02	CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE	Core crystal clock cycles when this thread is unhalted and the other thread is halted.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	25003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0x3c	0x08	CPU_CLK_UNHALTED.REF_DISTRIBUTED	Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0x40	0x01	SW_PREFETCH_ACCESS.NTA	Number of PREFETCHNTA instructions executed.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x40	0x02	SW_PREFETCH_ACCESS.T0	Number of PREFETCHT0 instructions executed.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x40	0x04	SW_PREFETCH_ACCESS.T1_T2	Number of PREFETCHT1 or PREFETCHT2 instructions executed.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x40	0x08	SW_PREFETCH_ACCESS.PREFETCHW	Number of PREFETCHW instructions executed.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x40	0xF	SW_PREFETCH_ACCESS.ANY	Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x42	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x43	0xfd	MEM_LOAD_COMPLETED.L1_MISS_ANY	Completed demand load uops that miss the L1 d-cache.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x44	0x01	MEM_STORE_RETIRED.L2_HIT	MEM_STORE_RETIRED.L2_HIT	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0x47	0x02	MEMORY_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	5	0x253	0	0	0	0	0	0	0	0	0	0x00
0x47	0x03	MEMORY_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	5	0x353	0	0	0	0	0	0	0	0	0	0x00
0x47	0x05	MEMORY_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss demand cacheable load request is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	5	0x553	0	0	0	0	0	0	0	0	0	0x00
0x47	0x09	MEMORY_ACTIVITY.STALLS_L3_MISS	Execution stalls while L3 cache miss demand cacheable load request is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	5	0x953	0	0	0	0	0	0	0	0	0	0x00
0x48	0x01	L1D_PEND_MISS.PENDING	Number of L1D misses that are outstanding	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x48	0x02	L1D_PEND_MISS.FB_FULL	Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x48	0x02	L1D_PEND_MISS.FB_FULL_PERIODS	Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	0x00
0x48	0x04	L1D_PEND_MISS.L2_STALLS	Number of cycles a demand request has waited due to L1D due to lack of L2 resources.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x4c	0x01	LOAD_HIT_PREFETCH.SWPF	Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x51	0x01	L1D.REPLACEMENT	Counts the number of cache lines replaced in L1 data cache.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x51	0x20	L1D.HWPF_MISS	L1D.HWPF_MISS	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x60	0x01	BACLEARS.ANY	Clears due to Unknown Branches.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x61	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	DSB-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x75	0x01	INST_DECODED.DECODERS	Instruction decoders utilized in a cycle	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x76	0x01	UOPS_DECODED.DEC0_UOPS	Number of non dec-by-all uops decoded by decoder	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x79	0x04	IDQ.MITE_CYCLES_ANY	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x79	0x04	IDQ.MITE_CYCLES_OK	Cycles MITE is delivering optimal number of Uops	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x79	0x08	IDQ.DSB_CYCLES_ANY	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x79	0x08	IDQ.DSB_CYCLES_OK	Cycles DSB is delivering optimal number of Uops	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x79	0x20	IDQ.MS_CYCLES_ANY	Cycles when uops are being delivered to IDQ while MS is busy	0,1,2,3	0,1,2,3	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0x79	0x20	IDQ.MS_SWITCHES	Number of switches from DSB or MITE to the MS	0,1,2,3	0,1,2,3	100003	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	0x00
0x79	0x20	IDQ.MS_UOPS	Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x80	0x04	ICACHE_DATA.STALLS	Cycles where a code fetch is stalled due to L1 instruction cache miss.	0,1,2,3	0,1,2,3	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x80	0x04	ICACHE_DATA.STALL_PERIODS	ICACHE_DATA.STALL_PERIODS	0,1,2,3	0,1,2,3	500009	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	0x00
0x83	0x04	ICACHE_TAG.STALLS	Cycles where a code fetch is stalled due to L1 instruction cache tag miss.	0,1,2,3	0,1,2,3	200003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x87	0x01	DECODE.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x87	0x02	DECODE.MS_BUSY	Cycles the Microcode Sequencer is busy.	0,1,2,3	0,1,2,3	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered by IDQ when backend of the machine is not stalled	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_BUBBLES.CORE	This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE	Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0x9c	0x01	IDQ_BUBBLES.CYCLES_FE_WAS_OK	Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	0x00
0xa2	0x02	RESOURCE_STALLS.SCOREBOARD	Counts cycles where the pipeline is stalled due to serializing operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x02	CYCLE_ACTIVITY.CYCLES_L3_MISS	Cycles while L3 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x453	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x553	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x06	CYCLE_ACTIVITY.STALLS_L3_MISS	Execution stalls while L3 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0x853	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x0c	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	0	2	0	0	0xC53	0	0	0	0	0	0	0	0	0	0x00
0xa3	0x10	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x1053	0	0	0	0	0	0	0	0	0	0x00
0xa4	0x01	TOPDOWN.SLOTS_P	TMA slots available for an unhalted logical processor. General counter - architectural event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa4	0x02	TOPDOWN.BACKEND_BOUND_SLOTS	This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa4	0x04	TOPDOWN.BAD_SPEC_SLOTS	TMA slots wasted due to incorrect speculations.	0	0	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa4	0x08	TOPDOWN.BR_MISPREDICT_SLOTS	TMA slots wasted due to incorrect speculation by branch mispredictions	0	0	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xa4	0x10	TOPDOWN.MEMORY_BOUND_SLOTS	TOPDOWN.MEMORY_BOUND_SLOTS	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	10000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa5	0x01	RS.EMPTY_RESOURCE	Cycles when RS was empty and a resource allocation stall is asserted	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa5	0x07	RS.EMPTY	Cycles when Reservation Station (RS) is empty for the thread.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa5	0x07	RS.EMPTY_COUNT	Counts end of periods where the Reservation Station (RS) was empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x1D7	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x02	EXE_ACTIVITY.1_PORTS_UTIL	Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x04	EXE_ACTIVITY.2_PORTS_UTIL	Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x08	EXE_ACTIVITY.3_PORTS_UTIL	Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x10	EXE_ACTIVITY.4_PORTS_UTIL	Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x21	EXE_ACTIVITY.BOUND_ON_LOADS	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x553	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x40	EXE_ACTIVITY.BOUND_ON_STORES	Cycles where the Store Buffer was full and no loads caused an execution stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	0x00
0xa6	0x80	EXE_ACTIVITY.EXE_BOUND_0_PORTS	Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa6	0xC	EXE_ACTIVITY.2_3_PORTS_UTIL	Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xa8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xa8	0x01	LSD.CYCLES_OK	Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x653	0	0	0	0	0	0	0	0	0	0x00
0xa8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xad	0x01	INT_MISC.RECOVERY_CYCLES	Core cycles the allocator was stalled due to recovery from earlier clear event for this thread	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xad	0x01	INT_MISC.CLEARS_COUNT	Clears speculative count	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	500009	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	0x00
0xad	0x10	INT_MISC.UOP_DROPPING	TMA slots where uops got dropped	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xad	0x40	INT_MISC.UNKNOWN_BRANCH_CYCLES	Bubble cycles of BAClear (Unknown Branch).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F7	0x7	0	2	1	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xad	0x80	INT_MISC.CLEAR_RESTEER_CYCLES	Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	500009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xae	0x01	UOPS_ISSUED.ANY	Uops that RAT issues to RS	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xae	0x01	UOPS_ISSUED.CYCLES	UOPS_ISSUED.CYCLES	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb0	0x01	ARITH.FPDIV_ACTIVE	This event counts the cycles the floating point divider is busy.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb0	0x08	ARITH.IDIV_ACTIVE	This event counts the cycles the integer divider is busy.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb0	0x09	ARITH.DIV_ACTIVE	Cycles when divide unit is busy executing divide or square root operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.CYCLES_GE_1	Cycles where at least 1 uop was executed per-thread	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.CYCLES_GE_2	Cycles where at least 2 uops were executed per-thread	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.CYCLES_GE_3	Cycles where at least 3 uops were executed per-thread	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x353	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.CYCLES_GE_4	Cycles where at least 4 uops were executed per-thread	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x453	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x01	UOPS_EXECUTED.STALLS	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x253	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x353	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x453	0	0	0	0	0	0	0	0	0	0x00
0xb1	0x10	UOPS_EXECUTED.X87	Counts the number of x87 uops dispatched.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x01	UOPS_DISPATCHED.PORT_0	Uops executed on port 0	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x02	UOPS_DISPATCHED.PORT_1	Uops executed on port 1	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x04	UOPS_DISPATCHED.PORT_2_3_10	Uops executed on ports 2, 3 and 10	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x10	UOPS_DISPATCHED.PORT_4_9	Uops executed on ports 4 and 9	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x20	UOPS_DISPATCHED.PORT_5_11	Uops executed on ports 5 and 11	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x40	UOPS_DISPATCHED.PORT_6	Uops executed on port 6	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb2	0x80	UOPS_DISPATCHED.PORT_7_8	Uops executed on ports 7 and 8	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x01	FP_ARITH_DISPATCHED.PORT_0	FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x01	FP_ARITH_DISPATCHED.V0	FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x02	FP_ARITH_DISPATCHED.PORT_1	FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x02	FP_ARITH_DISPATCHED.V1	FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x04	FP_ARITH_DISPATCHED.PORT_5	FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xb3	0x04	FP_ARITH_DISPATCHED.V2	FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter - architectural event	0,1,2,3,4,5,6,7	1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	NA	0x00
0xc0	0x02	INST_RETIRED.NOP	Retired NOP instructions.	0,1,2,3,4,5,6,7	1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x08	INST_RETIRED.REP_ITERATION	Iterations of Repeat string retired instructions.	0,1,2,3,4,5,6,7	1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc0	0x10	INST_RETIRED.MACRO_FUSED	INST_RETIRED.MACRO_FUSED	0,1,2,3,4,5,6,7	1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc1	0x02	ASSISTS.FP	Counts all microcode FP assists.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc1	0x08	ASSISTS.PAGE_FAULT	ASSISTS.PAGE_FAULT	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc1	0x10	ASSISTS.SSE_AVX_MIX	ASSISTS.SSE_AVX_MIX	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc1	0x1b	ASSISTS.ANY	Number of occurrences where a microcode assist is invoked by hardware.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x01	UOPS_RETIRED.HEAVY	Retired uops except the last uop of each instruction.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x02	UOPS_RETIRED.SLOTS	This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x02	UOPS_RETIRED.STALLS	Cycles without actually retired uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x1D3	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x02	UOPS_RETIRED.CYCLES	Cycles with retired uop(s).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	0x00
0xc2	0x04	UOPS_RETIRED.MS	UOPS_RETIRED.MS	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x3F7	0x8	0	2	1	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x157	0	0	0	0	0	0	0	0	0	0x00
0xc3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Number of machine clears due to memory ordering conflicts.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x01	BR_INST_RETIRED.COND_TAKEN	Taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x10	BR_INST_RETIRED.COND_NTAKEN	Not taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x11	BR_INST_RETIRED.COND	Conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc4	0x80	BR_INST_RETIRED.INDIRECT	Indirect near branch instructions retired (excluding returns)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x01	BR_MISP_RETIRED.COND_TAKEN	number of branch instructions retired that were mispredicted and taken.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x02	BR_MISP_RETIRED.INDIRECT_CALL	Mispredicted indirect CALL retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x08	BR_MISP_RETIRED.RET	This event counts the number of mispredicted ret instructions retired. Non PEBS	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x10	BR_MISP_RETIRED.COND_NTAKEN	Mispredicted non-taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x11	BR_MISP_RETIRED.COND	Mispredicted conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	Number of near branch instructions retired that were mispredicted and taken.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x41	BR_MISP_RETIRED.COND_TAKEN_COST	Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x42	BR_MISP_RETIRED.INDIRECT_CALL_COST	Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x44	BR_MISP_RETIRED.ALL_BRANCHES_COST	All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x48	BR_MISP_RETIRED.RET_COST	Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x50	BR_MISP_RETIRED.COND_NTAKEN_COST	Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x51	BR_MISP_RETIRED.COND_COST	Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x60	BR_MISP_RETIRED.NEAR_TAKEN_COST	Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0x80	BR_MISP_RETIRED.INDIRECT	Miss-predicted near indirect branch instructions retired (excluding returns)	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc5	0xc0	BR_MISP_RETIRED.INDIRECT_COST	Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xc6	0x02	FRONTEND_RETIRED.MISP_ANT	Mispredicted Retired ANT branches	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x9	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.DSB_MISS	Retired Instructions who experienced a critical DSB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x11	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.ITLB_MISS	Retired Instructions who experienced iTLB true miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x14	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.L1I_MISS	Retired Instructions who experienced Instruction L1 Cache true miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x12	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.L2_MISS	Retired Instructions who experienced Instruction L2 Cache true miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x13	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_1	Retired instructions after front-end starvation of at least 1 cycle	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x600106	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_128	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x608006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_16	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x601006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_2	Retired instructions after front-end starvation of at least 2 cycles	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x600206	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1	Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x100206	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_256	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x610006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_32	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x602006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_4	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x600406	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_512	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x620006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_64	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x604006	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.LATENCY_GE_8	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x600806	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.STLB_MISS	Retired Instructions who experienced STLB (2nd level TLB) true miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x15	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.UNKNOWN_BRANCH	FRONTEND_RETIRED.UNKNOWN_BRANCH	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x17	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.MS_FLOWS	FRONTEND_RETIRED.MS_FLOWS	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x8	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.ANY_DSB_MISS	Retired Instructions who experienced DSB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x1	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc6	0x03	FRONTEND_RETIRED.ANY_ANT	Retired ANT branches	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100007	0x3F7	0x9	1	2	1	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x01	FP_ARITH_INST_RETIRED.SCALAR_DOUBLE	Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x02	FP_ARITH_INST_RETIRED.SCALAR_SINGLE	Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x03	FP_ARITH_INST_RETIRED.SCALAR	Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x04	FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE	Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x08	FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x10	FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE	Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x18	FP_ARITH_INST_RETIRED.4_FLOPS	Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0x20	FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE	Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xc7	0xfc	FP_ARITH_INST_RETIRED.VECTOR	Number of any Vector retired FP arithmetic instructions	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xcc	0x20	MISC_RETIRED.LBR_INSERTS	Increments whenever there is an update to the LBR array.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	100003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	1009	0x3F6	0x80	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	20011	0x3F6	0x10	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	503	0x3F6	0x100	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	100007	0x3F6	0x20	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	100003	0x3F6	0x4	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	101	0x3F6	0x200	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	2003	0x3F6	0x40	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	50021	0x3F6	0x8	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024	Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	53	0x3F6	0x400	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048	Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.	1,2,3,4,5,6,7	1,2,3,4,5,6,7	23	0x3F6	0x800	1	2	1	0	0x53	1	0	0	1	0	0	0	0	0	0x00
0xcd	0x02	MEM_TRANS_RETIRED.STORE_SAMPLE	Retired memory store access operations. A PDist event for PEBS Store Latency Facility.	0	0	1000003	0x00	0x00	1	2	0	5	0x53	1	0	0	1	0	0	0	0	0	0x00
0xd0	0x09	MEM_INST_RETIRED.STLB_HIT_LOADS	Retired load instructions that hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x0a	MEM_INST_RETIRED.STLB_HIT_STORES	Retired store instructions that hit the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0x00
0xd0	0x11	MEM_INST_RETIRED.STLB_MISS_LOADS	Retired load instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x12	MEM_INST_RETIRED.STLB_MISS_STORES	Retired store instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0x00
0xd0	0x21	MEM_INST_RETIRED.LOCK_LOADS	Retired load instructions with locked access.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x41	MEM_INST_RETIRED.SPLIT_LOADS	Retired load instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x42	MEM_INST_RETIRED.SPLIT_STORES	Retired store instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0x00
0xd0	0x81	MEM_INST_RETIRED.ALL_LOADS	Retired load instructions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd0	0x82	MEM_INST_RETIRED.ALL_STORES	Retired store instructions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0x00
0xd0	0x83	MEM_INST_RETIRED.ANY	All retired memory instructions.	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	1	0	0	0	0	0x00
0xd1	0x01	MEM_LOAD_RETIRED.L1_HIT	Retired load instructions with L1 cache hits as data sources	0,1,2,3	0,1,2,3	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x02	MEM_LOAD_RETIRED.L2_HIT	Retired load instructions with L2 cache hits as data sources	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x04	MEM_LOAD_RETIRED.L3_HIT	Retired load instructions with L3 cache hits as data sources	0,1,2,3	0,1,2,3	100021	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x08	MEM_LOAD_RETIRED.L1_MISS	Retired load instructions missed L1 cache as data sources	0,1,2,3	0,1,2,3	200003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x10	MEM_LOAD_RETIRED.L2_MISS	Retired load instructions missed L2 cache as data sources	0,1,2,3	0,1,2,3	100021	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x20	MEM_LOAD_RETIRED.L3_MISS	Retired load instructions missed L3 cache as data sources	0,1,2,3	0,1,2,3	50021	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd1	0x40	MEM_LOAD_RETIRED.FB_HIT	Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd2	0x01	MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS	Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd2	0x02	MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD	Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd2	0x04	MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD	Retired load instructions whose data sources were HitM responses from shared L3	0,1,2,3	0,1,2,3	20011	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd2	0x08	MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE	Retired load instructions whose data sources were hits in L3 without snoops required	0,1,2,3	0,1,2,3	100003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd3	0x01	MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM	Retired load instructions which data sources missed L3 but serviced from local dram	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xd4	0x04	MEM_LOAD_MISC_RETIRED.UC	Retired instructions with at least 1 uncacheable load or lock.	0,1,2,3	0,1,2,3	100007	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0x00
0xe0	0x20	MISC2_RETIRED.LFENCE	LFENCE instructions retired	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe5	0x03	MEM_UOP_RETIRED.ANY	Retired memory uops for any access	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x03	INT_VEC_RETIRED.ADD_128	integer ADD, SUB, SAD 128-bit vector instructions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x0c	INT_VEC_RETIRED.ADD_256	integer ADD, SUB, SAD 256-bit vector instructions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x10	INT_VEC_RETIRED.VNNI_128	INT_VEC_RETIRED.VNNI_128	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x13	INT_VEC_RETIRED.128BIT	INT_VEC_RETIRED.128BIT	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x20	INT_VEC_RETIRED.VNNI_256	INT_VEC_RETIRED.VNNI_256	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x40	INT_VEC_RETIRED.SHUFFLES	INT_VEC_RETIRED.SHUFFLES	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0x80	INT_VEC_RETIRED.MUL_256	INT_VEC_RETIRED.MUL_256	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xe7	0xac	INT_VEC_RETIRED.256BIT	INT_VEC_RETIRED.256BIT	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xec	0x02	CPU_CLK_UNHALTED.DISTRIBUTED	Cycle counts are evenly distributed between active threads in the Core.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0x00
0xec	0x10	CPU_CLK_UNHALTED.C01	Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xec	0x20	CPU_CLK_UNHALTED.C02	Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xec	0x40	CPU_CLK_UNHALTED.PAUSE	CPU_CLK_UNHALTED.PAUSE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
0xec	0x40	CPU_CLK_UNHALTED.PAUSE_INST	CPU_CLK_UNHALTED.PAUSE_INST	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x157	0	0	0	0	0	0	0	0	0	0x00
0xec	0x70	CPU_CLK_UNHALTED.C0_WAIT	Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	0	0	0	0	0	0	0	0x00
