# Performance Monitoring Events for Intel perfmon version 5 Microarchitecture - V1
# Copyright (c) 2007 - 2020 Intel Corporation. All rights reserved.
CODE	UMASK	NAME	DESCRIPTION	COUNTER	COUNTER_HT_OFF	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	PRECISE_FE
0x00	0x01	INST_RETIRED.ANY	Number of instructions retired. Fixed Counter - architectural event	32	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0
0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state	33	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0
0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	34	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0
0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0
0xc0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter - architectural event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	0
0x3C	0x01	CPU_CLK_UNHALTED.REF_XCLK	Core crystal clock cycles when the thread is unhalted.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	25003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0
0xc4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	400009	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0
0xc5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	50021	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0
0xa4	0x01	TOPDOWN.SLOTS_P	TMA slots available for an unhalted logical processor. General counter - architectural event	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	10000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0
