# Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.24
# 07/18/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
iMC	0x03	0x01	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.RD_PCH0	DRAM Precharge commands. : Precharge due to read	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x02	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.WR_PCH0	DRAM Precharge commands. : Precharge due to write	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x04	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.UFILL_PCH0	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x08	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.PGT_PCH0	DRAM Precharge commands. : Precharges from Page Table	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x10	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.RD_PCH1	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x20	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.WR_PCH1	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x40	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.UFILL_PCH1	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x44	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.UFILL	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x03	0x80	0x00	0x00	0x00000000	UNC_M_PRE_COUNT.PGT_PCH1	DRAM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0x40	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.PCH0	DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0x80	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.PCH1	DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xc1	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.RD_REG	All DRAM read CAS commands issued (does not include underfills)	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xc2	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.RD_PRE_REG	DRAM RD_CAS and WR_CAS Commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xc4	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM underfill read CAS commands issued	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xc8	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.RD_PRE_UNDERFILL	DRAM RD_CAS and WR_CAS Commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xD0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.WR_NONPRE	DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x05	0xe0	0x00	0x00	0x00000000	UNC_M_CAS_COUNT.WR_PRE	DRAM RD_CAS and WR_CAS Commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0x40	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.PCH0	Pseudo Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0x80	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.PCH1	Pseudo Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xC1	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.RD_64B	Read CAS Command in Regular Mode (64B) in Pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xC2	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_64B	Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xC4	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.WR_64B	Write CAS Command in Regular Mode (64B) in Pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xC8	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.RD_32B	Read CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xD0	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_32B	Underfill Read CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x06	0xE0	0x00	0x00	0x00	UNC_M_CAS_ISSUED_REQ_LEN.WR_32B	Write CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x17	0x03	0x00	0x00	0x00000000	UNC_M_RDB_INSERTS	Counts the number of inserts into the read buffer destined for DDR.  Does not count reads destined for PMEM.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x18	0x01	0x00	0x00	0x00	UNC_M_RDB_NE.PCH0	Read Data Buffer Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x18	0x02	0x00	0x00	0x00	UNC_M_RDB_NE.PCH1	Read Data Buffer Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x18	0x03	0x00	0x00	0x00000000	UNC_M_RDB_NOT_EMPTY	Counts the number of cycles where there's at least one element in the read buffer.  This includes reads to both DDR and PMEM.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x18	0x03	0x00	0x00	0x00000000	UNC_M_RDB_NE	Counts the number of cycles where there's at least one element in the read buffer.  This includes reads to both DDR and PMEM.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x19	0x00	0x00	0x00	0x00000000	UNC_M_RDB_FULL	Counts the number of cycles where the read buffer has greater than UMASK elements.  This includes reads to both DDR and PMEM.  NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x1a	0x00	0x00	0x00	0x00000000	UNC_M_RDB_OCCUPANCY	Counts the number of elements in the read buffer, including reads to both DDR and PMEM.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x23	0x00	0x00000000	0x00000000	0x00000000	UNC_M_WPQ_READ_HIT	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x24	0x00	0x00000000	0x00000000	0x00000000	UNC_M_WPQ_WRITE_HIT	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x43	0x00	0x00	0x00	0x00000000	UNC_M_POWER_SELF_REFRESH	Clock-Enabled Self-Refresh	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x44	0x03	0x00	0x00	0x00	UNC_M_DRAM_PRE_ALL	DRAM Precharge All Commands	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x01	0x00	0x00	0x00000000	UNC_M_POWER_CKE_CYCLES.LOW_0	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x02	0x00	0x00	0x00000000	UNC_M_POWER_CKE_CYCLES.LOW_1	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x04	0x00	0x00	0x00000000	UNC_M_POWER_CKE_CYCLES.LOW_2	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x08	0x00	0x00	0x00000000	UNC_M_POWER_CKE_CYCLES.LOW_3	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x85	0x00	0x00	0x00	0x00000000	UNC_M_POWER_CHANNEL_PPD	Channel PPD Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x86	0x01	0x00	0x00	0x00000000	UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x86	0x02	0x00	0x00	0x00000000	UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xa0	0x05	0x00	0x00	0x00	UNC_M_PCLS.RD	UNC_M_PCLS.RD	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xa0	0x0a	0x00	0x00	0x00	UNC_M_PCLS.WR	UNC_M_PCLS.WR	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xa0	0x0f	0x00	0x00	0x00	UNC_M_PCLS.TOTAL	UNC_M_PCLS.TOTAL	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd0	0x00	0x00	0x00	0x00	UNC_M_SB_CYCLES_NE	Scoreboard Cycles Not-Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd1	0x00	0x00	0x00	0x00	UNC_M_SB_CYCLES_FULL	Scoreboard Cycles Full	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x01	0x00	0x00	0x00	UNC_M_SB_ACCESSES.RD_ACCEPTS	Scoreboard Accesses : Read Accepts	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x02	0x00	0x00	0x00	UNC_M_SB_ACCESSES.RD_REJECTS	Scoreboard Accesses : Read Rejects	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x04	0x00	0x00	0x00	UNC_M_SB_ACCESSES.WR_ACCEPTS	Scoreboard Accesses : NM read completions	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x05	0x00	0x00	0x00	UNC_M_SB_ACCESSES.ACCEPTS	Scoreboard accepts	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x08	0x00	0x00	0x00	UNC_M_SB_ACCESSES.WR_REJECTS	Scoreboard Accesses : NM write completions	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x0a	0x00	0x00	0x00	UNC_M_SB_ACCESSES.REJECTS	Scoreboard rejects	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x10	0x00	0x00	0x00	UNC_M_SB_ACCESSES.NM_RD_CMPS	Scoreboard Accesses : FM read completions	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x20	0x00	0x00	0x00	UNC_M_SB_ACCESSES.NM_WR_CMPS	Scoreboard Accesses : FM write completions	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x40	0x00	0x00	0x00	UNC_M_SB_ACCESSES.FM_RD_CMPS	Scoreboard Accesses : Write Accepts	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd2	0x80	0x00	0x00	0x00	UNC_M_SB_ACCESSES.FM_WR_CMPS	Scoreboard Accesses : Write Rejects	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd4	0x01	0x00	0x00	0x00	UNC_M_SB_REJECT.NM_SET_CNFLT	Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd4	0x02	0x00	0x00	0x00	UNC_M_SB_REJECT.FM_ADDR_CNFLT	Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd4	0x04	0x00	0x00	0x00	UNC_M_SB_REJECT.PATROL_SET_CNFLT	Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd4	0x08	0x00	0x00	0x00	UNC_M_SB_REJECT.CANARY	Number of Scoreboard Requests Rejected	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd4	0x20	0x00	0x00	0x00	UNC_M_SB_REJECT.DDR_EARLY_CMP	Number of Scoreboard Requests Rejected	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd5	0x01	0x00	0x00	0x00	UNC_M_SB_OCCUPANCY.RDS	Scoreboard Occupancy : Reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd5	0x04	0x00	0x00	0x00000000	UNC_M_SB_OCCUPANCY.PMM_RDS	Scoreboard Occupancy : Persistent Mem reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd5	0x08	0x00	0x00	0x00000000	UNC_M_SB_OCCUPANCY.PMM_WRS	Scoreboard Occupancy : Persistent Mem writes	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd5	0x20	0x00	0x00	0x00	UNC_M_SB_OCCUPANCY.BLOCK_RDS	Scoreboard Occupancy : Block region reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd5	0x40	0x00	0x00	0x00	UNC_M_SB_OCCUPANCY.BLOCK_WRS	Scoreboard Occupancy : Block region writes	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x01	0x00	0x00	0x00	UNC_M_SB_INSERTS.RDS	Scoreboard Inserts : Reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x02	0x00	0x00	0x00	UNC_M_SB_INSERTS.WRS	Scoreboard Inserts : Writes	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x04	0x00	0x00	0x00000000	UNC_M_SB_INSERTS.PMM_RDS	Scoreboard Inserts : Persistent Mem reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x08	0x00	0x00	0x00000000	UNC_M_SB_INSERTS.PMM_WRS	Scoreboard Inserts : Persistent Mem writes	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x10	0x00	0x00	0x00	UNC_M_SB_INSERTS.BLOCK_RDS	Scoreboard Inserts : Block region reads	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd6	0x20	0x00	0x00	0x00	UNC_M_SB_INSERTS.BLOCK_WRS	Scoreboard Inserts : Block region writes	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd7	0x01	0x00	0x00	0x00	UNC_M_SB_STRV_ALLOC.NM_RD	: Near Mem Read - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd7	0x02	0x00	0x00	0x00	UNC_M_SB_STRV_ALLOC.FM_RD	: Far Mem Read - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd7	0x04	0x00	0x00	0x00	UNC_M_SB_STRV_ALLOC.NM_WR	: Near Mem Write - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd7	0x08	0x00	0x00	0x00	UNC_M_SB_STRV_ALLOC.FM_WR	: Far Mem Write - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd7	0x10	0x00	0x00	0x00	UNC_M_SB_STRV_ALLOC.FM_TGR	: Near Mem Read - Clear	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd8	0x01	0x00	0x00	0x00	UNC_M_SB_STRV_OCC.NM_RD	: Near Mem Read	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd8	0x02	0x00	0x00	0x00	UNC_M_SB_STRV_OCC.FM_RD	: Far Mem Read	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd8	0x04	0x00	0x00	0x00	UNC_M_SB_STRV_OCC.NM_WR	: Near Mem Write	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd8	0x08	0x00	0x00	0x00	UNC_M_SB_STRV_OCC.FM_WR	: Far Mem Write	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd8	0x10	0x00	0x00	0x00	UNC_M_SB_STRV_OCC.FM_TGR	: Near Mem Read - Clear	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x01	0x00	0x00	0x00	UNC_M_SB_CANARY.ALLOC	: Alloc	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x02	0x00	0x00	0x00	UNC_M_SB_CANARY.DEALLOC	: Dealloc	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x04	0x00	0x00	0x00	UNC_M_SB_CANARY.VLD	: Reject	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x08	0x00	0x00	0x00	UNC_M_SB_CANARY.NM_RD_STARVED	: Valid	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x10	0x00	0x00	0x00	UNC_M_SB_CANARY.NM_WR_STARVED	: Near Mem Read Starved	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x20	0x00	0x00	0x00	UNC_M_SB_CANARY.FM_RD_STARVED	: Near Mem Write Starved	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x40	0x00	0x00	0x00	UNC_M_SB_CANARY.FM_WR_STARVED	: Far Mem Read Starved	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xd9	0x80	0x00	0x00	0x00	UNC_M_SB_CANARY.FM_TGR_WR_STARVED	: Far Mem Write Starved	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xda	0x01	0x00	0x00	0x00	UNC_M_SB_PREF_INSERTS.ALL	Scoreboard Prefetch Inserts : All	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xda	0x02	0x00	0x00	0x00000000	UNC_M_SB_PREF_INSERTS.DDR	Scoreboard Prefetch Inserts : DDR4	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xda	0x04	0x00	0x00	0x00000000	UNC_M_SB_PREF_INSERTS.PMM	Scoreboard Prefetch Inserts : PMM	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdb	0x01	0x00	0x00	0x00	UNC_M_SB_PREF_OCCUPANCY.ALL	Scoreboard Prefetch Occupancy : All	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdb	0x02	0x00	0x00	0x00	UNC_M_SB_PREF_OCCUPANCY.DDR	Scoreboard Prefetch Occupancy : DDR4	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xDB	0x04	0x00000000	0x00000000	0x00000000	UNC_M_SB_PREF_OCCUPANCY.PMM	Scoreboard Prefetch Occupancy : Persistent Mem	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x01	0x00	0x00	0x00	UNC_M_SB_TAGGED.NEW	UNC_M_SB_TAGGED.NEW	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x02	0x00	0x00	0x00	UNC_M_SB_TAGGED.RD_HIT	UNC_M_SB_TAGGED.RD_HIT	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x04	0x00	0x00	0x00	UNC_M_SB_TAGGED.RD_MISS	UNC_M_SB_TAGGED.RD_MISS	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x08	0x00	0x00	0x00	UNC_M_SB_TAGGED.DDR4_CMP	UNC_M_SB_TAGGED.DDR4_CMP	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x10	0x00	0x00	0x00000000	UNC_M_SB_TAGGED.PMM0_CMP	UNC_M_SB_TAGGED.PMM0_CMP	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x20	0x00	0x00	0x00000000	UNC_M_SB_TAGGED.PMM1_CMP	UNC_M_SB_TAGGED.PMM1_CMP	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x40	0x00	0x00	0x00000000	UNC_M_SB_TAGGED.PMM2_CMP	UNC_M_SB_TAGGED.PMM2_CMP	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xdd	0x80	0x00	0x00	0x00	UNC_M_SB_TAGGED.OCC	UNC_M_SB_TAGGED.OCC	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xde	0x01	0x00	0x00	0x00	UNC_M_SB_STRV_DEALLOC.NM_RD	: Near Mem Read - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xde	0x02	0x00	0x00	0x00	UNC_M_SB_STRV_DEALLOC.FM_RD	: Far Mem Read - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xde	0x04	0x00	0x00	0x00	UNC_M_SB_STRV_DEALLOC.NM_WR	: Near Mem Write - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xde	0x08	0x00	0x00	0x00	UNC_M_SB_STRV_DEALLOC.FM_WR	: Far Mem Write - Set	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xde	0x10	0x00	0x00	0x00	UNC_M_SB_STRV_DEALLOC.FM_TGR	: Near Mem Read - Clear	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xe0	0x04	0x00	0x00	0x00000000	UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0	PMM Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xe0	0x08	0x00	0x00	0x00000000	UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1	PMM Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xE0	0x10	0x00	0x00	0x00000000	UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0	PMM Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xE0	0x20	0x00	0x00	0x00000000	UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1	PMM Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xe4	0x0c	0x00	0x00	0x00	UNC_M_PMM_WPQ_OCCUPANCY.CAS	PMM (for IXP) Write Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xe4	0x30	0x00	0x00	0x00	UNC_M_PMM_WPQ_OCCUPANCY.PWR	PMM (for IXP) Write Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xe5	0x00	0x00	0x00	0x00000000	UNC_M_PMM_WPQ_CYCLES_NE	PMM (for IXP) Write Queue Cycles Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
