# Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.24
# 07/18/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
MCHBM	0x01	0x00	0x00	0x00	0x00000000	UNC_MCHBM_HCLOCKTICKS	IMC Clockticks at HCLK frequency	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x01	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.RD_PCH0	HBM Activate Count : Activate due to Read in PCH0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x02	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.WR_PCH0	HBM Activate Count : Activate due to Write in PCH0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x04	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.UFILL_PCH0	HBM Activate Count	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x10	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.RD_PCH1	HBM Activate Count : Activate due to Read in PCH1	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x11	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.RD	Activate due to read	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x20	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.WR_PCH1	HBM Activate Count : Activate due to Write in PCH1	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x22	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.WR	Activate due to write	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x40	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.UFILL_PCH1	HBM Activate Count	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0x44	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.UFILL	HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x02	0xff	0x00	0x00	0x00000000	UNC_MCHBM_ACT_COUNT.ALL	Activate due to read, write, underfill, or bypass	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x01	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.RD_PCH0	HBM Precharge commands. : Precharge due to read	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x02	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.WR_PCH0	HBM Precharge commands. : Precharge due to write	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x04	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.UFILL_PCH0	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x08	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.PGT_PCH0	HBM Precharge commands. : Precharges from Page Table	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x10	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.RD_PCH1	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x11	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.RD	Precharge due to read on page miss	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x20	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.WR_PCH1	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x22	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.WR	Precharge due to write on page miss	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x40	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.UFILL_PCH1	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x44	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.UFILL	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x80	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.PGT_PCH1	HBM Precharge commands.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0x88	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.PGT	Precharge from MC page table	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x03	0xff	0x00	0x00	0x00000000	UNC_MCHBM_PRE_COUNT.ALL	All precharge events	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0x40	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.PCH0	Pseudo Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0x80	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.PCH1	Pseudo Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xc1	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.RD_REG	Regular read CAS commands issued (does not include underfills)	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xc2	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.RD_PRE_REG	Regular read CAS commands with precharge	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xc4	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.RD_UNDERFILL	Underfill read CAS commands issued	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xc8	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.RD_PRE_UNDERFILL	Underfill read CAS commands with precharge	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xcf	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.RD	Read CAS commands issued (regular and underfill)	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xd0	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.WR_NONPRE	HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xe0	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.WR_PRE	Write CAS commands with precharge	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xf0	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.WR	Write CAS commands issued	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x05	0xff	0x00	0x00	0x00000000	UNC_MCHBM_CAS_COUNT.ALL	All CAS commands issued	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0x40	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH0	Pseudo Channel 0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0x80	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH1	Pseudo Channel 1	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xc1	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_64B	Read CAS Command in Regular Mode (64B) in Pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xc2	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_64B	Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xc4	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_64B	Write CAS Command in Regular Mode (64B) in Pseudochannel 0	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xc8	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_32B	Read CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xd0	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_32B	Underfill Read CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x06	0xe0	0x00	0x00	0x00	UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_32B	Write CAS Command in Interleaved Mode (32B)	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x10	0x01	0x00	0x00	0x00000000	UNC_MCHBM_RPQ_INSERTS.PCH0	Read Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x10	0x02	0x00	0x00	0x00000000	UNC_MCHBM_RPQ_INSERTS.PCH1	Read Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x17	0x01	0x00	0x00	0x00000000	UNC_MCHBM_RDB_INSERTS.PCH0	Read Data Buffer Inserts	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x17	0x02	0x00	0x00	0x00000000	UNC_MCHBM_RDB_INSERTS.PCH1	Read Data Buffer Inserts	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x17	0x03	0x00	0x00	0x00000000	UNC_MCHBM_RDB_INSERTS	Counts the number of inserts into the read buffer.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x19	0x00	0x00	0x00	0x00000000	UNC_MCHBM_RDB_FULL	Counts the number of cycles where the read buffer has greater than UMASK elements.  NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x1a	0x00	0x00	0x00	0x00000000	UNC_MCHBM_RDB_OCCUPANCY	Counts the number of elements in the read buffer per cycle.	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x20	0x01	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_INSERTS.PCH0	Write Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x20	0x02	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_INSERTS.PCH1	Write Pending Queue Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x23	0x00	0x00000000	0x00000000	0x00000000	UNC_MCHBM_WPQ_READ_HIT	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x23	0x01	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_READ_HIT.PCH0	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x23	0x02	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_READ_HIT.PCH1	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x24	0x00	0x00000000	0x00000000	0x00000000	UNC_MCHBM_WPQ_WRITE_HIT	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x24	0x01	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_WRITE_HIT.PCH0	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x24	0x02	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_WRITE_HIT.PCH1	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x44	0x01	0x00	0x00	0x00000000	UNC_MCHBM_HBM_PREALL.PCH0	HBM Precharge All Commands	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x44	0x02	0x00	0x00	0x00000000	UNC_MCHBM_HBM_PREALL.PCH1	HBM Precharge All Commands	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x44	0x03	0x00	0x00	0x00	UNC_MCHBM_HBM_PRE_ALL	All Precharge Commands	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x80	0x00	0x00	0x00	0x00000000	UNC_MCHBM_RPQ_OCCUPANCY_PCH0	Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x81	0x00	0x00	0x00	0x00000000	UNC_MCHBM_RPQ_OCCUPANCY_PCH1	Read Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x82	0x00	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_OCCUPANCY_PCH0	Write Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
MCHBM	0x83	0x00	0x00	0x00	0x00000000	UNC_MCHBM_WPQ_OCCUPANCY_PCH1	Write Pending Queue Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
