# Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.24
# 07/18/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
MDF	0x15	0x01	0x00	0x00	0x00000000	UNC_MDF_FAST_ASSERTED.AD_BNC	Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x15	0x02	0x00	0x00	0x00000000	UNC_MDF_FAST_ASSERTED.BL_CRD	Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x01	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.AD_BNC	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AD Bounceable)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x02	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.AD_CRD	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AD credited)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x04	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.BL_BNC	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (BL Bounceable)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x08	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.BL_CRD	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (BL credited)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x10	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.AK	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AK)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x20	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.IV	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (IV)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x47	0x40	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_INSERTS.AKC	Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AKC)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x4B	0x01	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_V_BOUNCES.AD	Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x4B	0x02	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_V_BOUNCES.BL	Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x4B	0x04	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_V_BOUNCES.AK	Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x4B	0x08	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_V_BOUNCES.IV	Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV)	0,1,2,3	na	0	0	0x00	PGMABLE
MDF	0x4B	0x10	0x00	0x00	0x00000000	UNC_MDF_CRS_TxR_V_BOUNCES.AKC	Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC)	0,1,2,3	na	0	0	0x00	PGMABLE
