# Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.24
# 07/18/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
UPI LL	0x02	0x01	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT0	Valid Flits Sent : Slot 0	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x02	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT1	Valid Flits Sent : Slot 1	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x04	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.SLOT2	Valid Flits Sent : Slot 2	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x08	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.DATA	Valid Flits Sent : Data	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x10	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.LLCRD	Valid Flits Sent : LLCRD Not Empty	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x17	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.ALL_LLCRD	Valid Flits Sent : All LLCRD Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x20	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.NULL	Valid Flits Sent : Slot NULL or LLCRD Empty	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x40	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.LLCTRL	Valid Flits Sent : LLCTRL	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x47	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.IDLE	Valid Flits Sent : Idle	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x47	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.ALL_LLCTRL	Valid Flits Sent : All LLCTRL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x02	0x80	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.PROTHDR	Valid Flits Sent : Protocol Header	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x02	0x87	0x00	0x00	0x00000000	UNC_UPI_TxL_FLITS.ALL_PROTHDR	Valid Flits Sent : All Protocol Header	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT0	Valid Flits Received : Slot 0	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT1	Valid Flits Received : Slot 1	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.SLOT2	Valid Flits Received : Slot 2	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x08	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.DATA	Valid Flits Received : Data	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x10	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.LLCRD	Valid Flits Received : LLCRD Not Empty	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x20	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.NULL	Valid Flits Received : Slot NULL or LLCRD Empty	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x40	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.LLCTRL	Valid Flits Received : LLCTRL	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x03	0x47	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.IDLE	Valid Flits Received : Idle	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x03	0x80	0x00	0x00	0x00000000	UNC_UPI_RxL_FLITS.PROTHDR	Valid Flits Received : Protocol Header	0,1,2,3	na	0	0	0x02	PGMABLE
UPI LL	0x04	0x0e	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB	Matches on Transmit path of a UPI Port : Non-Coherent Bypass	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x04	0x0e	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x04	0x0f	0x00	0x00	0x00000000	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS	Matches on Transmit path of a UPI Port : Non-Coherent Standard	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x04	0x0f	0x00	0x00	0x00000001	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x05	0x0e	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB	Matches on Receive path of a UPI Port : Non-Coherent Bypass	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x05	0x0e	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x05	0x0f	0x00	0x00	0x00000000	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS	Matches on Receive path of a UPI Port : Non-Coherent Standard	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x05	0x0f	0x00	0x00	0x00000001	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode	0,1,2,3	CtrCtrl[55:32]	0	0	0x00	PGMABLE
UPI LL	0x08	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT	LLR Requests Sent	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x0b	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL_CRC_ERRORS	CRC Errors Detected	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x12	0x01	0x00	0x00	0x00000000	UNC_UPI_DIRECT_ATTEMPTS.D2C	Direct packet attempts : D2C	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x12	0x02	0x00	0x00	0x00000000	UNC_UPI_DIRECT_ATTEMPTS.D2K	Direct packet attempts : D2K	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x14	0x01	0x00	0x00	0x00000000	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x14	0x02	0x00	0x00	0x00000000	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x14	0x04	0x00	0x00	0x00000000	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x14	0x08	0x00	0x00	0x00000000	UNC_UPI_M3_BYP_BLOCKED.BGF_CRD	UNC_UPI_M3_BYP_BLOCKED.BGF_CRD	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x14	0x10	0x00	0x00	0x00000000	UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK	UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x01	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x02	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x04	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x08	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x10	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x20	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD	UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x15	0x40	0x00	0x00	0x00000000	UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK	UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x16	0x00	0x00	0x00	0x00000000	UNC_UPI_M3_CRD_RETURN_BLOCKED	UNC_UPI_M3_CRD_RETURN_BLOCKED	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x01	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x02	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x04	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x08	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x10	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x20	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x40	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x18	0x80	0x00	0x00	0x00000000	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x20	0x00	0x00	0x00	0x00000000	UNC_UPI_PHY_INIT_CYCLES	Cycles where phy is not in L0, L0c, L0p, L1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x22	0x00	0x00	0x00	0x00000000	UNC_UPI_POWER_L1_REQ	L1 Req (same as L1 Ack).	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x23	0x00	0x00	0x00	0x00000000	UNC_UPI_POWER_L1_NACK	L1 Req Nack	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x24	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL0_POWER_CYCLES	Cycles in L0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x25	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL0P_POWER_CYCLES	Cycles in L0p	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x26	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0_POWER_CYCLES	Cycles in L0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x27	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES	Cycles in L0p	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x28	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x29	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x01	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL	UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x02	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x04	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x08	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x10	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.TXQ	UNC_UPI_TxL0P_CLK_ACTIVE.TXQ	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x20	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.RETRY	UNC_UPI_TxL0P_CLK_ACTIVE.RETRY	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x40	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.DFX	UNC_UPI_TxL0P_CLK_ACTIVE.DFX	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x2a	0x80	0x00	0x00	0x00000000	UNC_UPI_TxL0P_CLK_ACTIVE.SPARE	UNC_UPI_TxL0P_CLK_ACTIVE.SPARE	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT0	RxQ Flit Buffer Allocations : Slot 0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT1	RxQ Flit Buffer Allocations : Slot 1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x30	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_INSERTS.SLOT2	RxQ Flit Buffer Allocations : Slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x31	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_BYPASSED.SLOT0	RxQ Flit Buffer Bypassed : Slot 0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x31	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_BYPASSED.SLOT1	RxQ Flit Buffer Bypassed : Slot 1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x31	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_BYPASSED.SLOT2	RxQ Flit Buffer Bypassed : Slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT0	RxQ Occupancy - All Packets : Slot 0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT1	RxQ Occupancy - All Packets : Slot 1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x32	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_OCCUPANCY.SLOT2	RxQ Occupancy - All Packets : Slot 2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x08	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x10	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x33	0x20	0x00	0x00	0x00000000	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x38	0x00	0x00000000	0x00000000	0x00000000	UNC_UPI_RxL_CREDITS_CONSUMED_VNA	VNA Credit Consumed	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x39	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL_CREDITS_CONSUMED_VN0	VN0 Credit Consumed	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x3a	0x00	0x00	0x00	0x00000000	UNC_UPI_RxL_CREDITS_CONSUMED_VN1	VN1 Credit Consumed	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x40	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL_INSERTS	Tx Flit Buffer Allocations	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x41	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL_BYPASSED	Tx Flit Buffer Bypassed	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x42	0x00	0x00	0x00	0x00000000	UNC_UPI_TxL_OCCUPANCY	Tx Flit Buffer Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x44	0x00	0x00	0x00	0x00000000	UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY	VNA Credits Pending Return - Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x45	0x00	0x00	0x00	0x00000000	UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01	UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x46	0x01	0x00	0x00	0x00000000	UNC_UPI_REQ_SLOT2_FROM_M3.VNA	UNC_UPI_REQ_SLOT2_FROM_M3.VNA	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x46	0x02	0x00	0x00	0x00000000	UNC_UPI_REQ_SLOT2_FROM_M3.VN0	UNC_UPI_REQ_SLOT2_FROM_M3.VN0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x46	0x04	0x00	0x00	0x00000000	UNC_UPI_REQ_SLOT2_FROM_M3.VN1	UNC_UPI_REQ_SLOT2_FROM_M3.VN1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x46	0x08	0x00	0x00	0x00000000	UNC_UPI_REQ_SLOT2_FROM_M3.ACK	UNC_UPI_REQ_SLOT2_FROM_M3.ACK	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x01	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.SLOT0	UNC_UPI_TxL_ANY_FLITS.SLOT0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x02	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.SLOT1	UNC_UPI_TxL_ANY_FLITS.SLOT1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x04	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.SLOT2	UNC_UPI_TxL_ANY_FLITS.SLOT2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x08	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.DATA	UNC_UPI_TxL_ANY_FLITS.DATA	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x10	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.LLCRD	UNC_UPI_TxL_ANY_FLITS.LLCRD	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x20	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.NULL	UNC_UPI_TxL_ANY_FLITS.NULL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x40	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.LLCTRL	UNC_UPI_TxL_ANY_FLITS.LLCTRL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4A	0x80	0x00	0x00	0x00000000	UNC_UPI_TxL_ANY_FLITS.PROTHDR	UNC_UPI_TxL_ANY_FLITS.PROTHDR	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x01	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.SLOT0	UNC_UPI_RxL_ANY_FLITS.SLOT0	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x02	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.SLOT1	UNC_UPI_RxL_ANY_FLITS.SLOT1	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x04	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.SLOT2	UNC_UPI_RxL_ANY_FLITS.SLOT2	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x08	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.DATA	UNC_UPI_RxL_ANY_FLITS.DATA	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x10	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.LLCRD	UNC_UPI_RxL_ANY_FLITS.LLCRD	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x20	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.NULL	UNC_UPI_RxL_ANY_FLITS.NULL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x40	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.LLCTRL	UNC_UPI_RxL_ANY_FLITS.LLCTRL	0,1,2,3	na	0	0	0x00	PGMABLE
UPI LL	0x4B	0x80	0x00	0x00	0x00000000	UNC_UPI_RxL_ANY_FLITS.PROTHDR	UNC_UPI_RxL_ANY_FLITS.PROTHDR	0,1,2,3	na	0	0	0x00	PGMABLE
