# Performance Monitoring Events for Intel(R) Xeon(R) Processor Scalable Family based on Skylake microarchitecture - V1.35
# 04/03/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS
PCU	0x0	0x0	0x00	0x00	0x00	UNC_P_CLOCKTICKS	pclk Cycles	0,1,2,3	na	0	0	0x00
PCU	0x2A	0x0	0x00	0x00	0x00	UNC_P_PKG_RESIDENCY_C0_CYCLES	Package C State Residency - C0	0,1,2,3	na	0	0	0x00
PCU	0x2B	0x0	0x00	0x00	0x00	UNC_P_PKG_RESIDENCY_C2E_CYCLES	Package C State Residency - C2E	0,1,2,3	na	0	0	0x00
PCU	0x2C	0x0	0x00	0x00	0x00	UNC_P_PKG_RESIDENCY_C3_CYCLES	Package C State Residency - C3	0,1,2,3	na	0	0	0x00
PCU	0x2D	0x0	0x00	0x00	0x00	UNC_P_PKG_RESIDENCY_C6_CYCLES	Package C State Residency - C6	0,1,2,3	na	0	0	0x00
PCU	0x2F	0x0	0x00	0x00	0x00	UNC_P_MEMORY_PHASE_SHEDDING_CYCLES	Memory Phase Shedding Cycles	0,1,2,3	na	0	0	0x00
PCU	0x30	0x0	0x00	0x00	0x00	UNC_P_DEMOTIONS	UNC_P_DEMOTIONS	0,1,2,3	na	0	0	0x00
PCU	0x4	0x0	0x00	0x00	0x00	UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES	Thermal Strongest Upper Limit Cycles	0,1,2,3	na	0	0	0x00
PCU	0x42	0x0	0x00	0x00	0x00	UNC_P_VR_HOT_CYCLES	VR Hot	0,1,2,3	na	0	0	0x00
PCU	0x5	0x0	0x00	0x00	0x00	UNC_P_FREQ_MAX_POWER_CYCLES	Power Strongest Upper Limit Cycles	0,1,2,3	na	0	0	0x00
PCU	0x6	0x0	0x00	0x00	0x00	UNC_P_MCP_PROCHOT_CYCLES	UNC_P_MCP_PROCHOT_CYCLES	0,1,2,3	na	0	0	0x00
PCU	0x60	0x0	0x00	0x00	0x00	UNC_P_CORE_TRANSITION_CYCLES	UNC_P_CORE_TRANSITION_CYCLES	0,1,2,3	na	0	0	0x00
PCU	0x7	0x0	0x00	0x00	0x00	UNC_P_PMAX_THROTTLED_CYCLES	UNC_P_PMAX_THROTTLED_CYCLES	0,1,2,3	na	0	0	0x00
PCU	0x72	0x0	0x00	0x00	0x00	UNC_P_TOTAL_TRANSITION_CYCLES	Total Core C State Transition Cycles	0,1,2,3	na	0	0	0x00
PCU	0x73	0x0	0x00	0x00	0x00	UNC_P_FREQ_MIN_IO_P_CYCLES	IO P Limit Strongest Lower Limit Cycles	0,1,2,3	na	0	0	0x00
PCU	0x74	0x0	0x00	0x00	0x00	UNC_P_FREQ_TRANS_CYCLES	Cycles spent changing Frequency	0,1,2,3	na	0	0	0x00
PCU	0x75	0x0	0x00	0x00	0x00	UNC_P_FIVR_PS_PS0_CYCLES	Phase Shed 0 Cycles	0,1,2,3	na	0	0	0x00
PCU	0x76	0x0	0x00	0x00	0x00	UNC_P_FIVR_PS_PS1_CYCLES	Phase Shed 1 Cycles	0,1,2,3	na	0	0	0x00
PCU	0x77	0x0	0x00	0x00	0x00	UNC_P_FIVR_PS_PS2_CYCLES	Phase Shed 2 Cycles	0,1,2,3	na	0	0	0x00
PCU	0x78	0x0	0x00	0x00	0x00	UNC_P_FIVR_PS_PS3_CYCLES	Phase Shed 3 Cycles	0,1,2,3	na	0	0	0x00
PCU	0x80	0x40	0x00	0x00	0x00	UNC_P_POWER_STATE_OCCUPANCY.CORES_C0	Number of cores in C-State; C0 and C1	0,1,2,3	na	0	0	0x00
PCU	0x80	0x80	0x00	0x00	0x00	UNC_P_POWER_STATE_OCCUPANCY.CORES_C3	Number of cores in C-State; C3	0,1,2,3	na	0	0	0x00
PCU	0x80	0xC0	0x00	0x00	0x00	UNC_P_POWER_STATE_OCCUPANCY.CORES_C6	Number of cores in C-State; C6 and C7	0,1,2,3	na	0	0	0x00
PCU	0x9	0x0	0x00	0x00	0x00	UNC_P_PROCHOT_INTERNAL_CYCLES	Internal Prochot	0,1,2,3	na	0	0	0x00
PCU	0xA	0x0	0x00	0x00	0x00	UNC_P_PROCHOT_EXTERNAL_CYCLES	External Prochot	0,1,2,3	na	0	0	0x00
