# Performance Monitoring Events for Intel(R) Xeon(R) Processor Scalable Family based on Skylake microarchitecture - V1.35
# 04/03/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS
UPI LL	0x14	0x1	0x00	0x00	0x00	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2	0,1,2,3	na	0	0	0x00
UPI LL	0x14	0x10	0x00	0x00	0x00	UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK	UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK	0,1,2,3	na	0	0	0x00
UPI LL	0x14	0x2	0x00	0x00	0x00	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x14	0x4	0x00	0x00	0x00	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3	UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3	0,1,2,3	na	0	0	0x00
UPI LL	0x14	0x8	0x00	0x00	0x00	UNC_UPI_M3_BYP_BLOCKED.BGF_CRD	UNC_UPI_M3_BYP_BLOCKED.BGF_CRD	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x1	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x10	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x2	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x20	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD	UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x4	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x40	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK	UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK	0,1,2,3	na	0	0	0x00
UPI LL	0x15	0x8	0x00	0x00	0x00	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH	UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH	0,1,2,3	na	0	0	0x00
UPI LL	0x16	0x0	0x00	0x00	0x00	UNC_UPI_M3_CRD_RETURN_BLOCKED	UNC_UPI_M3_CRD_RETURN_BLOCKED	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x02	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x04	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x1	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x10	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x20	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x40	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x8	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0	UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x18	0x80	0x00	0x00	0x00	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3	UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3	0,1,2,3	na	0	0	0x00
UPI LL	0x2	0x1	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.SLOT0	Valid Flits Sent; Slot 0	0,1,2,3	na	0	0	0x02
UPI LL	0x2	0x10	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.LLCRD	Valid Flits Sent; LLCRD Not Empty	0,1,2,3	na	0	0	0x02
UPI LL	0x2	0x2	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.SLOT1	Valid Flits Sent; Slot 1	0,1,2,3	na	0	0	0x02
UPI LL	0x2	0x4	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.SLOT2	Valid Flits Sent; Slot 2	0,1,2,3	na	0	0	0x02
UPI LL	0x2	0x40	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.LLCTRL	Valid Flits Sent; LLCTRL	0,1,2,3	na	0	0	0x02
UPI LL	0x2	0x80	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.PROT_HDR	This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR	0,1,2,3	na	0	0	0x03
UPI LL	0x2	0x80	0x00	0x00	0x00	UNC_UPI_TxL_FLITS.PROTHDR	Valid Flits Sent; Protocol Header	0,1,2,3	na	0	0	0x00
UPI LL	0x20	0x0	0x00	0x00	0x00	UNC_UPI_PHY_INIT_CYCLES	Cycles where phy is not in L0, L0c, L0p, L1	0,1,2,3	na	0	0	0x00
UPI LL	0x22	0x0	0x00	0x00	0x00	UNC_UPI_POWER_L1_REQ	L1 Req (same as L1 Ack).	0,1,2,3	na	0	0	0x00
UPI LL	0x23	0x0	0x00	0x00	0x00	UNC_UPI_POWER_L1_NACK	L1 Req Nack	0,1,2,3	na	0	0	0x00
UPI LL	0x24	0x0	0x00	0x00	0x00	UNC_UPI_RxL0_POWER_CYCLES	Cycles in L0. Receive side.	0,1,2,3	na	0	0	0x00
UPI LL	0x26	0x0	0x00	0x00	0x00	UNC_UPI_TxL0_POWER_CYCLES	Cycles in L0. Transmit side.	0,1,2,3	na	0	0	0x00
UPI LL	0x28	0x0	0x00	0x00	0x00	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER	0,1,2,3	na	0	0	0x00
UPI LL	0x29	0x0	0x00	0x00	0x00	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x1	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL	UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x10	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.TXQ	UNC_UPI_TxL0P_CLK_ACTIVE.TXQ	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x2	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x20	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.RETRY	UNC_UPI_TxL0P_CLK_ACTIVE.RETRY	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x4	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x40	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.DFX	UNC_UPI_TxL0P_CLK_ACTIVE.DFX	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x8	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED	UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED	0,1,2,3	na	0	0	0x00
UPI LL	0x2A	0x80	0x00	0x00	0x00	UNC_UPI_TxL0P_CLK_ACTIVE.SPARE	UNC_UPI_TxL0P_CLK_ACTIVE.SPARE	0,1,2,3	na	0	0	0x00
UPI LL	0x3	0x1	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.SLOT0	Valid Flits Received; Slot 0	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x10	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.LLCRD	Valid Flits Received; LLCRD Not Empty	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x2	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.SLOT1	Valid Flits Received; Slot 1	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x4	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.SLOT2	Valid Flits Received; Slot 2	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x40	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.LLCTRL	Valid Flits Received; LLCTRL	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x47	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.IDLE	Valid Flits Received; Idle	0,1,2,3	na	0	0	0x00
UPI LL	0x3	0x8	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.DATA	Valid Flits Received; Data	0,1,2,3	na	0	0	0x02
UPI LL	0x3	0x80	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.PROT_HDR	This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR	0,1,2,3	na	0	0	0x03
UPI LL	0x3	0x80	0x00	0x00	0x00	UNC_UPI_RxL_FLITS.PROTHDR	Valid Flits Received; Protocol Header	0,1,2,3	na	0	0	0x00
UPI LL	0x30	0x01	0x00	0x00	0x00	UNC_UPI_RxL_INSERTS.SLOT0	RxQ Flit Buffer Allocations; Slot 0	0,1,2,3	na	0	0	0x00
UPI LL	0x30	0x02	0x00	0x00	0x00	UNC_UPI_RxL_INSERTS.SLOT1	RxQ Flit Buffer Allocations; Slot 1	0,1,2,3	na	0	0	0x00
UPI LL	0x30	0x04	0x00	0x00	0x00	UNC_UPI_RxL_INSERTS.SLOT2	RxQ Flit Buffer Allocations; Slot 2	0,1,2,3	na	0	0	0x00
UPI LL	0x32	0x1	0x00	0x00	0x00	UNC_UPI_RxL_OCCUPANCY.SLOT0	RxQ Occupancy - All Packets; Slot 0	0,1,2,3	na	0	0	0x00
UPI LL	0x32	0x2	0x00	0x00	0x00	UNC_UPI_RxL_OCCUPANCY.SLOT1	RxQ Occupancy - All Packets; Slot 1	0,1,2,3	na	0	0	0x00
UPI LL	0x32	0x4	0x00	0x00	0x00	UNC_UPI_RxL_OCCUPANCY.SLOT2	RxQ Occupancy - All Packets; Slot 2	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x1	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x10	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x2	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2	UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x20	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1	UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x4	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0	0,1,2,3	na	0	0	0x00
UPI LL	0x33	0x8	0x00	0x00	0x00	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2	UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2	0,1,2,3	na	0	0	0x00
UPI LL	0x38	0x0	0x00	0x00	0x00	UNC_UPI_RxL_CREDITS_CONSUMED_VNA	VNA Credit Consumed	0,1,2,3	na	0	0	0x00
UPI LL	0x39	0x0	0x00	0x00	0x00	UNC_UPI_RxL_CREDITS_CONSUMED_VN0	VN0 Credit Consumed	0,1,2,3	na	0	0	0x00
UPI LL	0x3A	0x0	0x00	0x00	0x00	UNC_UPI_RxL_CREDITS_CONSUMED_VN1	VN1 Credit Consumed	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0	0x00	0x00	0x02	UNC_UPI_TxL_HDR_MATCH.LOC	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x0	0x00	0x00	0x04	UNC_UPI_TxL_HDR_MATCH.REM	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x0	0x00	0x00	0x08	UNC_UPI_TxL_HDR_MATCH.DATA_HDR	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x0	0x00	0x00	0x10	UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x0	0x00	0x00	0x20	UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x0	0x00	0x00	0x40	UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR	This event is deprecated.	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x08	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.REQ	Matches on Transmit path of a UPI Port; Request	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x08	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC	Matches on Transmit path of a UPI Port; Request Opcode	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x09	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.SNP	Matches on Transmit path of a UPI Port; Snoop	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x09	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC	Matches on Transmit path of a UPI Port; Snoop Opcode	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x0A	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA	Matches on Transmit path of a UPI Port; Response - No Data	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0A	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC	Matches on Transmit path of a UPI Port; Response - No Data	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x0C	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA	Matches on Transmit path of a UPI Port; Response - Data	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0C	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC	Matches on Transmit path of a UPI Port; Response - Data	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x0D	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.WB	Matches on Transmit path of a UPI Port; Writeback	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0D	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC	Matches on Transmit path of a UPI Port; Writeback	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x0E	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB	Matches on Transmit path of a UPI Port; Non-Coherent Bypass	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0E	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Transmit path of a UPI Port; Non-Coherent Bypass	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x0F	0x00	0x00	0x0	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS	Matches on Transmit path of a UPI Port; Non-Coherent Standard	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x0F	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Transmit path of a UPI Port; Non-Coherent Standard	0,1,2,3	na	0	0	0x02
UPI LL	0x4	0x2A	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI	Matches on Transmit path of a UPI Port; Response - Invalid	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0x8	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.REQ	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0x9	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.SNP	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0xA	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.RSP_NODATA	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0xAA	0x00	0x00	0x1	UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT	Matches on Transmit path of a UPI Port; Response - Conflict	0,1,2,3	na	0	0	0x00
UPI LL	0x4	0xC	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.WB	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0xC	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.RSP_DATA	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0xE	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.NCB	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB	0,1,2,3	na	0	0	0x01
UPI LL	0x4	0xF	0x00	0x00	0x00	UNC_UPI_TxL_HDR_MATCH.NCS	This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS	0,1,2,3	na	0	0	0x01
UPI LL	0x40	0x0	0x00	0x00	0x00	UNC_UPI_TxL_INSERTS	Tx Flit Buffer Allocations	0,1,2,3	na	0	0	0x00
UPI LL	0x42	0x0	0x00	0x00	0x00	UNC_UPI_TxL_OCCUPANCY	Tx Flit Buffer Occupancy	0,1,2,3	na	0	0	0x00
UPI LL	0x44	0x0	0x00	0x00	0x00	UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY	VNA Credits Pending Return - Occupancy	0,1,2,3	na	0	0	0x00
UPI LL	0x45	0x0	0x00	0x00	0x00	UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01	UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01	0,1,2,3	na	0	0	0x00
UPI LL	0x46	0x1	0x00	0x00	0x00	UNC_UPI_REQ_SLOT2_FROM_M3.VNA	UNC_UPI_REQ_SLOT2_FROM_M3.VNA	0,1,2,3	na	0	0	0x00
UPI LL	0x46	0x2	0x00	0x00	0x00	UNC_UPI_REQ_SLOT2_FROM_M3.VN0	UNC_UPI_REQ_SLOT2_FROM_M3.VN0	0,1,2,3	na	0	0	0x00
UPI LL	0x46	0x4	0x00	0x00	0x00	UNC_UPI_REQ_SLOT2_FROM_M3.VN1	UNC_UPI_REQ_SLOT2_FROM_M3.VN1	0,1,2,3	na	0	0	0x00
UPI LL	0x46	0x8	0x00	0x00	0x00	UNC_UPI_REQ_SLOT2_FROM_M3.ACK	UNC_UPI_REQ_SLOT2_FROM_M3.ACK	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x08	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.REQ	Matches on Receive path of a UPI Port; Request	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x08	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC	Matches on Receive path of a UPI Port; Request Opcode	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x09	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.SNP	Matches on Receive path of a UPI Port; Snoop	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x09	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC	Matches on Receive path of a UPI Port; Snoop Opcode	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x0A	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA	Matches on Receive path of a UPI Port; Response - No Data	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x0A	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC	Matches on Receive path of a UPI Port; Response - No Data	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x0C	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA	Matches on Receive path of a UPI Port; Response - Data	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x0C	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC	Matches on Receive path of a UPI Port; Response - Data	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x0D	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.WB	Matches on Receive path of a UPI Port; Writeback	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x0D	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC	Matches on Receive path of a UPI Port; Writeback	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x0E	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB	Matches on Receive path of a UPI Port; Non-Coherent Bypass	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x0E	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC	Matches on Receive path of a UPI Port; Non-Coherent Bypass	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x0F	0x00	0x00	0x00	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS	Matches on Receive path of a UPI Port; Non-Coherent Standard	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x0F	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC	Matches on Receive path of a UPI Port; Non-Coherent Standard	0,1,2,3	na	0	0	0x02
UPI LL	0x5	0x2A	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI	Matches on Receive path of a UPI Port; Response - Invalid	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0x8	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.REQ	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ	0,1,2,3	na	0	0	0x01
UPI LL	0x5	0x9	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.SNP	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP	0,1,2,3	na	0	0	0x01
UPI LL	0x5	0xA	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.RSP	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA	0,1,2,3	na	0	0	0x01
UPI LL	0x5	0xAA	0x00	0x00	0x01	UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT	Matches on Receive path of a UPI Port; Response - Conflict	0,1,2,3	na	0	0	0x00
UPI LL	0x5	0xB	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.WB	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB	0,1,2,3	na	0	0	0x01
UPI LL	0x5	0xC	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.NCB	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB	0,1,2,3	na	0	0	0x01
UPI LL	0x5	0xD	0x00	0x00	0x00	UNC_UPI_RxL_HDR_MATCH.NCS	This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS	0,1,2,3	na	0	0	0x01
UPI LL	0x8	0x0	0x00	0x00	0x00	UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT	LLR Requests Sent	0,1,2,3	na	0	0	0x00
UPI LL	0xB	0x0	0x00	0x00	0x00	UNC_UPI_RxL_CRC_ERRORS	CRC Errors Detected	0,1,2,3	na	0	0	0x00
