# Performance Monitoring Events for Intel Atom(R) Processors based on SnowRidge microarchitecture - V1.23
# 04/24/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	PORT_MASK	FC_MASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	FILTER	INTERNAL	FILTER_VALUE	EVENT_STATUS	COUNTER_TYPE
iMC	0x00	0x00	0x00	0x00	0x00	UNC_M_CLOCKTICKS_FREERUN	Free running counter that increments for the Memory Controller	4	na	0	0	0x00	FREERUN
iMC	0x01	0x08	0x00	0x00	0x00	UNC_M_ACT_COUNT.BYP	DRAM Activate Count : Activate due to Bypass	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x02	0x0c	0x00	0x00	0x00	UNC_M_PRE_COUNT.PAGE_MISS	DRAM Precharge commands. : Precharge due to page miss	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x01	0x00	0x00	0x00	UNC_M_CAS_COUNT.RD_REG	All DRAM read CAS commands issued (does not include underfills)	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x02	0x00	0x00	0x00	UNC_M_CAS_COUNT.RD_PRE_REG	DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x04	0x00	0x00	0x00	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM underfill read CAS commands issued	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x08	0x00	0x00	0x00	UNC_M_CAS_COUNT.RD_PRE_UNDERFILL	DRAM RD_CAS and WR_CAS Commands.	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x10	0x00	0x00	0x00	UNC_M_CAS_COUNT.WR_NONPRE	DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x04	0x20	0x00	0x00	0x00	UNC_M_CAS_COUNT.WR_PRE	DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x11	0x01	0x00	0x00	0x00	UNC_M_RPQ_CYCLES_NE.PCH0	Read Pending Queue Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x11	0x02	0x00	0x00	0x00	UNC_M_RPQ_CYCLES_NE.PCH1	Read Pending Queue Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x12	0x00	0x00	0x00	0x00	UNC_M_RPQ_CYCLES_FULL_PCH0	Read Pending Queue Full Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x15	0x00	0x00	0x00	0x00	UNC_M_RPQ_CYCLES_FULL_PCH1	Read Pending Queue Full Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x16	0x00	0x00	0x00	0x00	UNC_M_WPQ_CYCLES_FULL_PCH1	Write Pending Queue Full Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x17	0x00	0x00	0x00	0x00	UNC_M_RDB_INSERTS	Read Data Buffer Inserts	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x18	0x00	0x00	0x00	0x00	UNC_M_RDB_NOT_EMPTY	Read Data Buffer Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x19	0x00	0x00	0x00	0x00	UNC_M_RDB_FULL	Read Data Buffer Full	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x1A	0x00	0x00	0x00	0x00	UNC_M_RDB_OCCUPANCY	Read Data Buffer Occupancy	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x21	0x01	0x00	0x00	0x00	UNC_M_WPQ_CYCLES_NE.PCH0	Write Pending Queue Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x21	0x02	0x00	0x00	0x00	UNC_M_WPQ_CYCLES_NE.PCH1	Write Pending Queue Not Empty	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x22	0x00	0x00	0x00	0x00	UNC_M_WPQ_CYCLES_FULL_PCH0	Write Pending Queue Full Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x23	0x01	0x00	0x00	0x00	UNC_M_WPQ_READ_HIT.PCH0	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x23	0x02	0x00	0x00	0x00	UNC_M_WPQ_READ_HIT.PCH1	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x24	0x01	0x00	0x00	0x00	UNC_M_WPQ_WRITE_HIT.PCH0	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x24	0x02	0x00	0x00	0x00	UNC_M_WPQ_WRITE_HIT.PCH1	Write Pending Queue CAM Match	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x2c	0x00	0x00	0x00	0x00	UNC_M_PARITY_ERRORS	UNC_M_PARITY_ERRORS	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x43	0x00	0x00	0x00	0x00	UNC_M_POWER_SELF_REFRESH	Clock-Enabled Self-Refresh	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x44	0x00	0x00	0x00	0x00	UNC_M_DRAM_PRE_ALL	DRAM Precharge All Commands	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x46	0x01	0x00	0x00	0x00	UNC_M_POWER_THROTTLE_CYCLES.SLOT0	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x46	0x02	0x00	0x00	0x00	UNC_M_POWER_THROTTLE_CYCLES.SLOT1	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x01	0x00	0x00	0x00	UNC_M_POWER_CKE_CYCLES.LOW_0	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x02	0x00	0x00	0x00	UNC_M_POWER_CKE_CYCLES.LOW_1	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x04	0x00	0x00	0x00	UNC_M_POWER_CKE_CYCLES.LOW_2	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x47	0x08	0x00	0x00	0x00	UNC_M_POWER_CKE_CYCLES.LOW_3	CKE_ON_CYCLES by Rank : DIMM ID	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x85	0x00	0x00	0x00	0x00	UNC_M_POWER_CHANNEL_PPD	Channel PPD Cycles	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x86	0x01	0x00	0x00	0x00	UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0x86	0x02	0x00	0x00	0x00	UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1	Throttle Cycles for Rank 0	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xA0	0x01	0x00	0x00	0x00	UNC_M_PCLS.RD	UNC_M_PCLS.RD	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xA0	0x02	0x00	0x00	0x00	UNC_M_PCLS.WR	UNC_M_PCLS.WR	0,1,2,3	na	0	0	0x00	PGMABLE
iMC	0xA0	0x04	0x00	0x00	0x00	UNC_M_PCLS.TOTAL	UNC_M_PCLS.TOTAL	0,1,2,3	na	0	0	0x00	PGMABLE
