##########################################################################
# SEP Uncore Event File: UNC_SOC_DDR_Self_Refresh.txt
# Copyright(c) 2014-2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Wed Aug 26 11:58:03 2014
# Target: TNG-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 75526
# GROUP_NAME       : UNC_SOC_DDR_Self_Refresh
# GROUP_DESC       : Counts the number of performance monitoring clock cycles that memory channel 0 and 1 are in self-refresh. The performance monitoring clock can be determined by UNC_VISA_CLK_CYCLES counts and self-refresh residency can be calculated as UNC_VISA_DDR_Self_Refresh/UNC_VISA_CLK_CYCLES.
# EVENT_ID         : 75514
# EVENT_NAME       : DDR_Chan0_Deep_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 0 is in deep self-refresh.
# EVENT_COUNTER    : 0
# EVENT_ID         : 75517
# EVENT_NAME       : DDR_Chan0_Shallow_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 0 is in shallow self-refresh.
# EVENT_COUNTER    : 1
# EVENT_ID         : 75520
# EVENT_NAME       : DDR_Chan1_Deep_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 1 is in deep self-refresh.
# EVENT_COUNTER    : 2
# EVENT_ID         : 75523
# EVENT_NAME       : DDR_Chan1_Shallow_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 1 is in shallow self-refresh.
# EVENT_COUNTER    : 3

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000904	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000900	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000908	0x00000102	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000090C	0x00000203	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000910	0x00000304	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000928	0x04003C00	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000092C	0x0000001F	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000930	0x00000000	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B804	0x00001011	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B800	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B808	0x00001112	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B80C	0x00001819	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B810	0x0000191A	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C884	0x00000005	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C880	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C888	0x00000004	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000CA84	0x00000005	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000CA80	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000CA88	0x00000004	0xFFFFFFFF	26	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000008	0x00FC01C2	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000000C	0x00FC02C2	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000010	0x00F304C2	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000014	0x00F308C2	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000018	0x000000C3	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000060	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000070	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000120	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000121	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00000122	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000005C	0x00000123	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000006C	0x00002124	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000064	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000074	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010120	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110121	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x02110122	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000058	0x02110123	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000068	0x00110000	0xFFFFFFFF	25	1
