##########################################################################
# SEP Uncore Event File: UNC_SOC_Memory_DDR_BW.txt
# Copyright(c) 2014-2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Wed Aug 20 11:58:03 2014
# Target: TNG-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 75101
# GROUP_NAME       : UNC_SOC_Memory_DDR_BW
# GROUP_DESC       : Counts requests to memory, for both memory channels. Determine memory bandwidth by multiplying event count by 32 bytes.
# EVENT_ID         : 74611
# EVENT_NAME       : DDR_Chan0-Read32B
# EVENT_DESC       : Counts memory read requests of size 32 bytes to memory channel 0.
# EVENT_COUNTER    : 0
# EVENT_ID         : 74631
# EVENT_NAME       : DDR_Chan0-Write32B
# EVENT_DESC       : Counts memory write requests of size 32 bytes to memory channel 0.
# EVENT_COUNTER    : 1
# EVENT_ID         : 74651
# EVENT_NAME       : DDR_Chan1-Read32B
# EVENT_DESC       : Counts memory read requests of size 32 bytes to memory channel 1.
# EVENT_COUNTER    : 2
# EVENT_ID         : 74671
# EVENT_NAME       : DDR_Chan1-Write32B
# EVENT_DESC       : Counts memory write requests of size 32 bytes to memory channel 1.
# EVENT_COUNTER    : 3

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000904	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000900	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000908	0x00000102	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000928	0x02400801	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000092C	0x0000000A	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000930	0x00000000	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B804	0x00001011	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B800	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000B808	0x00001819	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C884	0x00000002	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C880	0x00000001	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000CA84	0x00000002	0xFFFFFFFF	26	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000CA80	0x00000001	0xFFFFFFFF	26	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000060	0x10000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000100	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000101	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00000102	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000005C	0x00000103	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000064	0x00000000	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010100	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110101	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x02110102	0xFFFFFFFF	25	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000058	0x02110103	0xFFFFFFFF	25	1
