# Performance Monitoring Events for 11th Generation Intel(R) Core(TM) Processor - V1.16
# 04/05/2024 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	NAME	DESCRIPTION	COUNTER	EVENT_STATUS	COUNTER_TYPE
imc	0x00	0x00	UNC_MC0_TOTAL_REQCOUNT_FREERUN	Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.	0	0x00	FREERUN
imc	0x00	0x00	UNC_MC0_RDCAS_COUNT_FREERUN	Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.	1	0x00	FREERUN
imc	0x00	0x00	UNC_MC0_WRCAS_COUNT_FREERUN	Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.	2	0x00	FREERUN
imc	0x00	0x00	UNC_MC1_TOTAL_REQCOUNT_FREERUN	Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.	3	0x00	FREERUN
imc	0x00	0x00	UNC_MC1_RDCAS_COUNT_FREERUN	Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.	4	0x00	FREERUN
imc	0x00	0x00	UNC_MC1_WRCAS_COUNT_FREERUN	Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.	5	0x00	FREERUN
