##########################################################################
# SEP Uncore Event File: UNC_SOC_All_Reqs.txt
# Copyright(c) 2014-2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Thu Aug 21 14:11:51 2014
# Target: VLV-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 17803
# GROUP_NAME       : UNC_SOC_All_Reqs
# GROUP_DESC       : Counts the number of requests per memory agent. Counts can be used to identify high demand agents or to estimate bandwidth for an agent by multiplying each request by 64 bytes.
# EVENT_ID         : 17745
# EVENT_NAME       : Mod0_Reqs
# EVENT_DESC       : Counts the number of requests from Silvermont module 0.
# EVENT_COUNTER    : 0
# EVENT_ID         : 17749
# EVENT_NAME       : Mod1_Reqs
# EVENT_DESC       : Counts the number of requests from Silvermont module 1.
# EVENT_COUNTER    : 1
# EVENT_ID         : 17751
# EVENT_NAME       : GFX_Reqs
# EVENT_DESC       : Counts the number of requests from the graphics controller.
# EVENT_COUNTER    : 2
# EVENT_ID         : 17752
# EVENT_NAME       : Disp_Reqs
# EVENT_DESC       : Counts the number of requests from the display controller.
# EVENT_COUNTER    : 3
# EVENT_ID         : 17753
# EVENT_NAME       : Imaging_Reqs
# EVENT_DESC       : Counts the number of requests from the imaging controller.
# EVENT_COUNTER    : 4
# EVENT_ID         : 17754
# EVENT_NAME       : VED_Reqs
# EVENT_DESC       : Counts the number of requests from the video encode/decode controller.
# EVENT_COUNTER    : 5
# EVENT_ID         : 17978
# EVENT_NAME       : LowSpeedPF_Reqs
# EVENT_DESC       : Counts the aggregate number of requests from the low speed peripheral fabric.
# EVENT_COUNTER    : 6
# CLOCK_COUNTER    : 7

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x30000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C204	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C208	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x00000102	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A8	0x00C00400	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000AC	0x01801404	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B0	0x00002007	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B4	0x00000009	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B8	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000BC	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C04	0x00002728	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C00	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C08	0x00002829	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009904	0x00000A0B	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009900	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009908	0x00000B0C	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009884	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009880	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009888	0x00000002	0xFFFFFFFF	24	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000008	0x00FEFF20	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000000C	0x003FFF00	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000010	0x00FCFF10	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000014	0x00000003	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000060	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000070	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000090	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A0	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000100	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000101	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00000102	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000005C	0x00000103	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000006C	0x00000104	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000007C	0x00000105	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000008C	0x00000122	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000009C	0x00002123	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000064	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000074	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000094	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A4	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010100	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110101	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x02110102	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000058	0x02110103	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000068	0x02110104	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000078	0x02110105	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x02110122	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000098	0x00110000	0xFFFFFFFF	23	1
