##########################################################################
# SEP Uncore Event File: UNC_SOC_DDR_Self_Refresh.txt
# Copyright(c) 2014-2016 Intel Corporation. All rights reserved.
# File: PUBLIC
# Events: PUBLIC
# Created: Thu Aug 21 14:11:51 2014
# Target: VLV-B0
# Revision: 2.0-3.1.3.0
##########################################################################

# EVENT INFORMATION

# GROUP_ID         : 17802
# GROUP_NAME       : UNC_SOC_DDR_Self_Refresh
# GROUP_DESC       : Counts the number of performance monitoring clock cycles that memory channel 0 and 1 are in self-refresh. The performance monitoring clock can be determined by UNC_VISA_CLK_CYCLES counts and self-refresh residency can be calculated as UNC_VISA_DDR_Self_Refresh/UNC_VISA_CLK_CYCLES.
# EVENT_ID         : 17792
# EVENT_NAME       : DDR_Chan0_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 0 is in self-refresh.
# EVENT_COUNTER    : 0
# EVENT_ID         : 17795
# EVENT_NAME       : DDR_Chan1_Self_Refresh
# EVENT_DESC       : Counts the number of cycles that memory channel 1 is in self-refresh.
# EVENT_COUNTER    : 1
# CLOCK_COUNTER    : 2

# All SOC Programing
# HEADER	CFGTYPE	BUS_NUMBER	DEVICE_NUMBER	FUNC_NUMBER	REG_SIZE	OPERATION	BARNAME	OFFSET	VALUE	MASK	PORT_ID	OP_CODE
#<CFGTYPE-MMIO/PCICFG>	<BUS_NUMBER>	<DEVICE_NUMBER>	<FUNC_NUMBER>	<REGISTER_SIZE>	<READ/WRITE/RMW operation>	<BARNAME>	<OFFSET>	<VALUE>	<MASK>	<PORT_ID>	<OP_CODE>

# SOC CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x30000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C204	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000C208	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000084	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000080	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000088	0x00000102	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000A8	0x01401807	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000AC	0x0340380F	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x000000B0	0x00000000	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C04	0x00001F20	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C00	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009C08	0x00002021	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009D04	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009D00	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00009D08	0x00000607	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00008A04	0x0000007B	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00008A00	0x00000001	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00008A84	0x0000007B	0xFFFFFFFF	24	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00008A80	0x00000001	0xFFFFFFFF	24	1
# COUNTER CONFIGURATION

CFG	0	0	0	32	WRITE	SOCPCI	0x00000000	0x00008000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000008	0x00F8FFC0	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000000C	0x00C7FFC0	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000010	0x000000C3	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000030	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000040	0x10000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000050	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000002C	0x00000120	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000003C	0x00000121	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x0000004C	0x00002122	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000034	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000044	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000054	0x00000000	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000028	0x02010120	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000038	0x02110121	0xFFFFFFFF	23	1
CFG	0	0	0	32	WRITE	SOCPCI	0x00000048	0x00110000	0xFFFFFFFF	23	1
